MIPI C-PHY/D-PHY Combo Universal IP, 4.5Gsps/4.5Gbps in TSMC 22ULP
Getting started in structured assembly in complex SoC designs
By Tim Schneider, Arteris IP (July 27, 2022) - EDN
The integration level of a system-on-chip (SoC) is defined in RTL, just like the rest of the design. Historically, RTL has been built through text editors. However, a decade or more ago, the sheer complexity of that task for the largest SoCs became unmanageable; now, most SoCs cross that threshold. Why is this? The number of IPs in the SoC is certainly a factor, and the number of connections explodes at the integration level. For example, a single AXI channel connection can have 25 signals. Next, AMBA to AMBA connections in multiple flavors proliferate across designs.
Also, designers must include the integration infrastructure—clocks, resets, power management and test—which must evolve as the design progresses. These requirements can add up to 10,000 connections in an unexceptional SoC. Connections between IPs may have hundreds of ports with multiple configuration tie-off options. These ports may be left open or connected and have many other significant considerations. Typical interconnect complexity is evident even in a small subset of the design.
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