Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when the device is not active (leakage power). This highly competitive industry provides significant rewards for being the first to achieve best-in-class power efficiency in these markets. And of course, all of this must be achieved without impacting performance or area. Power, performance, and area (PPA) are the critical metrics for today’s advanced semiconductor SoCs.
Synopsys Foundation IP Memory Compilers and Logic Libraries enable SoC designers to achieve the best possible PPA, getting the maximum possible performance out of their designs while enabling them at the lowest possible operating voltages (near threshold values of transistors), thus significantly reducing overall power consumption. The result is longer battery life and higher Performance Per Watt.
In this paper we will discuss:
- Deep low voltage requirements (0.4v typical and below) for mobile, IoT, high performance compute (HPC), automotive, and crypto applications
- Various techniques adopted by SoC designers to trade-off PPA, including improvements on existing assist techniques for memory compilers
- Architectural and characterization enhancements to support lower voltages for logic libraries
- How Synopsys Memory Compilers and Logic Libraries have been enhanced to support deep low voltages to save power, while still achieving optimal performance and area and maintaining high reliability
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