Why network-on-chip IP in SoC must be physically aware
By Andy Nightingale, Arteris IP
EDN (February 10, 2023)
Today, multicore system-on-chip (SoC) designs can be composed of hundreds of IP blocks, typically containing up to ten million logic gates. One way for SoC developers to create devices of this complexity is to make use of proven IP blocks provided by trusted third-party vendors. There’s no point in devoting thousands of hours to reinventing a USB 3.2 Gen x interface, for example, when it is already available as off-the-shelf IP. Instead, engineers can focus their efforts on creating their own internal IP that will differentiate their SoC from any competitive offerings.
When it comes to connecting the IP blocks so they can talk to each other, the only practical option for the majority of today’s high-capacity and high-complexity SoCs is to use a network-on-chip (NoC). What many people fail to realize is that an NoC is IP too, albeit IP that spans the entire SoC. As for this IP, design teams can decide to develop the NoC in-house, or they can choose to use proven NoC IP from a trusted third-party vendor.
Another consideration SoC architects can easily overlook is the necessity for the NoC’s design environment to be physically aware. This dramatically accelerates the exploration of the needed space to achieve an optimal NoC topology at the front-end of the process. It also significantly speeds up timing closure at the back-end.
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