BIST, BISR tools push up quality, yield
BIST, BISR tools push up quality, yield
By Damien Chardonnereau, Senior Applications Engineer, iRoC Technologies, Santa Clara, Calif., Technologies , EE Times
April 28, 2003 (4:16 p.m. EST)
Today's nanometer system-on-chip (SoC) designs typically embed a very large number of memories that are extremely sensitive to many different hardware-production defects. These defects affect three key production and profitability targets: quality, yield and reliability. There are solutions available today, however, that will help manufacturers produce reliable, high-yield, high-quality SoC devices.
For many years, built-in self-test has been implemented in most embedded memories. Several good BIST-generation tools are currently on the market. BIST solutions help manufacturers reach the quality target, and are implemented to tackle quality at two levels.
At the production level, most SoC manufacturers try to achieve 100 percent fault coverage in order to deliver a high-quality SoC. Rising chip complexity, however, has led to an increase in the complexity of production defects. To reach the goal of increased fault coverage at this level, chip designers need to implement complex BIST algorithms.
A given BIST algorithm will detect a certain amount of defects. The most common types available are the March algorithms, which typically will detect major defect types such as address-decoder faults or stuck-at faults.
On the other hand, increasing chip and technology complexity has led to new defect types like stuck-open faults. Designers who implement March algorithms on most BIST generators may not necessarily detect these new defect types, since they only provide a fixed set of BIST algorithms. Designers need to use BIST synthesis tools to develop the user-defined algorithms that are able to cover the highest number of defect types.
At the technology level, new BIST algorithms are also needed to increase the fault coverage for a given process technology, since technology improvement leads to new defect types. In order to develop these new algorithms on high-end embedded memories, the test engineer needs to have the ability to change the algorithm on the production tester.
Since designers need to be able to modify the algorithm, the engineer will use programmable BIST to determine the most suitable test algorithm for the given process technology. As soon as the test algorithm is recognized as the most efficient algorithm, the designer will synthesize it for the next memory generation based on the process technology. This algorithm will be hard-coded into the memory. The programmability feature is available on very few BIST commercial tools and mostly at very high silicon cost. In spite of that cost, the programmable BIST is necessary to develop high-coverage BIST algorithms.
Mixed programmable synthesis BIST is a new BIST architecture that incorporates BIST algorithm synthesis as well as BIST programmability. This new architecture has the ability to implement custom high-wired BIST algorithms. It gives designers the choice of using the programmability feature on the programmabil ity feature on the production tester to improve the algorithm. At low silicon cost, this architecture meets the quality demands.
Yield is another concern. Increasing size, density and complexity in memory technologies lead to higher defect density and a decrease in yield. Following memory defect detection during memory test, a hardware laser repair step is added into the production flow to enhance the memory yield. Laser repair induces an extremely long test time and extra hardware costs, both at the silicon level and at the production level, where extra laser equipment is needed.
A cost- and time-effective solution is built-in self-repair (BISR). It consists of replacing, on-silicon, the defective memory columns by spare columns available next to the functional memory. BISR is implemented at the column, row, block or bit level. Using nonvolatile blocks to store the memory reconfiguration improves the memory production yield.
Reliability aspect is also considered by all th e chip manufacturers. High memory size and high-end memory technologies often lead to an increasing number of defects that happen during the product life. Such defects are incredibly expensive to tackle since they imply in-the-field debug. BISR solutions allow the memory to be tested in the field and the defective memory blocks to be replaced by redundant blocks that are not defective. If the memory contains critical contents, transparent BISR allows defective blocks to be tested and replaced without losing the original memory content. Such solutions, which ensure higher product reliability in the field, are available at low silicon cost.
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