English
Network-on-chip (NoC) interconnect topologies explained
By Andy Nightingale, ArterisIP (July 26, 2023)
Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks. Each IP block may have its own data width and clock frequency and employ one of the standard SoC interface protocols: OCP, APB, AHB, AXI, STBus, and DTL. Connecting all these IPs is a significant challenge.
Functional IP blocks connect to the network-on-chip (NoC) via sockets. In the case of an initiator IP, the socket serializes and packetizes the data generated by the IP, assigns an ID to the packet, and dispatches it into the network. When the packet arrives at its destination IP, the associated socket extracts the data from the packet and transforms it into the protocol required by the IP. A large number of packets can be in flight throughout the network at any given time.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Arteris Hot IP
Related Articles
New Articles
Most Popular
- System Verilog Assertions Simplified
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Dynamic Memory Allocation and Fragmentation in C and C++
- PCIe error logging and handling on a typical SoC
- Enhancing VLSI Design Efficiency: Tackling Congestion and Shorts with Practical Approaches and PnR Tool (ICC2)