FPGAs have a distinct advantage over ASICs in terms of nonrecurring engineering costs and verification methodology (there being none): Just run the chip on a test board and verify that it works. But the synthesis, place and route loop has taken its toll.
Traditionally, the FPGA designer has been a register-transfer level or logic designer who hasn't cared about place and route. That mind-set has led to 12-plus hours of a single iteration through the tool flow, with 50 or more iterations to close on each design. The only viable choice for the designer is to change the RTL code after each iteration.
But another way is emerging. Silicon virtual prototyping (SVP) provides a representation of the final design early in the design cycle, so the designer can comprehend, modify, verify and implement the design to meet constraint s. It can shorten the time-to-market through incremental physical design, hierarchical physical design, predictability and repeatability in the implementation flow, offering fewer performance-based iterations.
How is SVP technology for FPGA design different from that proposed in the ASIC world? The single most important difference is that FPGA SVP needs to understand the FPGA architecture extremely well.
FPGA SVP must be able to predict with sufficient accuracy the prelayout placement and routing structures that will be used to construct the netlist topology. This is challenging because most tra-ditional placement and routing algorithms assume that geometric proximity for all pins on nets is desirable. FPGA architectures are mostly represented as rows and columns of logic blocks. Utmost attention is paid in trying to keep delay through routes between two points on this logic-block matrix to correlate with the Manhattan distance between them.
But in reality, this is not the case. Buf fered interconnect and different route topologies-one that jumps two rows/columns over, as opposed to one that jumps six rows/columns over-make delay prediction extremely difficult. Geometric proximity, though desirable, does not guarantee superior results. Routability of a design can also be seriously hampered if too many heavily connected components are placed among geometrically close logic blocks.
Ideally, FPGA SVP would abstract those complexities and present a simpler, more understandable model of the design. With this model or prototype, the designer could make informed decisions about an implementation strategy. Long iteration loops between synthesis and place and route would be cut into a much shorter one between synthesis and silicon virtual prototyping.
A well-architected FPGA SVP tool could substantially reduce design time for ambitious FPGA designs and could close the chapter on ASICs as well.
SALIL RAJE is chief technology officer and vice president of engineering for Hi er Design Inc. (Santa Clara, Calif.).