FinFETs form the foundation for many of today’s semiconductor fabrication techniques but also create significant design concerns that affect your layout. Understanding the changes and design strategies that finFET requires is crucial to building an effective layout. In this post, we’ll talk about how these changes influence integrated circuit layout.
The Emergence of FinFET Technology
With each generation of integrated circuit technology, custom physical layout becomes more and more challenging. From the days of manually cutting shapes into Rubylith to today’s computer-aided design, layout rules have grown exponentially in number and complexity to accommodate the ever-increasing density of the underlying transistors.
For decades, planar complementary metal oxide semiconductor (CMOS) integrated chip (IC) technology followed the dictates of Moore’s Law and Dennard scaling. When physical limits started to make these trends falter in the early 2010s, there was only one way for planar CMOS to go: up. When that happened at the sub-20 nanometer (nm) nodes, layout design rules and techniques took an enormous leap in complexity and constraints.
FinFET Transistor Basics
A finFET — a type of field-effect transistor (FET) — can be envisioned as a traditional planar CMOS transistor turned on its side so that the gate polysilicon can interface with the source and drain on two surfaces. The vertical structure where transistor action occurs is called a “fin” and is fabricated from doped silicon.
The fins can be constructed on bulk silicon, in which case they must be isolated in much the same way as in planar CMOS. They can also be on top of an insulating layer as in silicon-on-insulator (SOI) CMOS. The gate poly is deposited such that it runs up one side of the fin, over the top, and down the other side. The channel is formed everywhere the poly contacts the fin.
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