Leveraging the RISC-V Efficient Trace (E-Trace) standard

By Iain Robertson, Senior Engineering Director, Tessent Embedded Analytics

Understanding program behaviour in complex systems is not easy. Understanding the behaviour of complete systems is even more challenging. Get non-intrusive, full-speed and system-level visibility with E-Trace.

Processor trace gives developers access to critical insights and forensic capabilities to manage the risk of building embedded systems.

Processor trace is a common non-intrusive debugging technique which many development teams and customers expect as a minimum feature of any SoC deliverable. Trace captures, encodes and transmits off-chip a record of executed processor instructions, which software tools can use to reconstruct the exact execution sequence of a program. Embedded developers can then inspect the execution sequence to verify the RISC-V instruction set architecture (ISA), debug application code, profile the processor and explore code coverage.

You can learn more about Tessent Efficient Trace for RISC-V (E-Trace) in this video presentation by Iain Roberston, Senior Director of hardware engineering, Tessent, recorded at RISC-V Summit North America in 2023, and in which he takes a detailed look at “Leveraging the RISC-V efficient trace (E-Trace) standard.”

Iain provides an expert insight into:

• Trace basics, including ways in which trace is commonly implemented
• An overview of the RISC-V Efficient trace (E-Trace) standard
• How processor trace is used to improve embedded software and applications, including a case study of how Seagate used E-Trace
• Comparisons of different E-Trace solutions

Watch now at: https://blogs.sw.siemens.com/tessent/2024/01/16/leveraging-the-risc-v-efficient-trace-e-trace-standard/

Learn more about Tessen’t RISC-V solutions.

About Tessent Embedded Analytics, Siemens EDA

Tessent Embedded Analytics dramatically reduces the Silicon debug effort and enables post-deployment analytics for RISC-V-based and other complex system-on-chips (SoCs).

The Tessent™ Enhanced Trace Encoder is a fully‑featured RISC‑V trace solution that provides a mechanism to monitor the program execution of a CPU in real time. It encodes program execution (instruction trace) and optionally, the data from load and store instructions (data trace), outputting trace in a highly compressed format. External software can later take this data and use it to reconstruct the program execution flow. The Tessent Enhanced Trace Encoder can be finely tuned to balance the features and gate-count requirements of your system and includes a broad range of filters, giving complete control over what and when to trace. It complies with the latest standards produced by the RISC‑V International’s Efficient Trace for RISC‑V (E‑Trace) Working Group, supporting any standards‑compliant RISC‑V processor.

In addition to a comprehensive range of on-chip analytic monitors, Tessent also provides the software to analyze and interpret the trace results, providing everything you need to ensure that your design is fully debugged when you need it to be. Using Tessent Embedded Analytics components, you can debug and trace any design from simple single‑processor systems to highly complex superscalar multi‑processor systems.