SoC goal staying alive: lowest cost, smallest size
SoC goal staying alive: lowest cost, smallest size
By Glenn Raskin, Distinguished Member of the Technical Staff, Keith Tilley, Principal Staff Engineer, Motorola Semiconductor Products Sector, Wireless & Broadband Systems Group, Phoenix, Ariz., EE Times
May 23, 2003 (9:58 a.m. EST)
As IC designers and architects race to achieve the promise of SoC Integration, we are seeing a "collision of two (or more) worlds" that historically had been handled by different engineering teams or even different companies. The goal of SoC is driving the combination of multiple functions, requiring heterogeneous processes (Flash vs. CMOS vs. SiGe) and design techniques (RF vs. analog vs. memory vs. processor cores). A great deal of focus has been placed on the architectural and semiconductor processing challenges as we integrate further and further. So, what is the appropriate packaging media for SoC devices?
Traditional RF devices have had small lead counts and coarse die pad pitches and the focus for wireless RF packaging has been for low inductance I/O, good current carrying capabilities, and excellent loss characteristics. For digital applications with relatively high lead counts, fine pad pitch and very dense pin arrays have been used . In the high end (>500 pin) devices, flip chip technology has been utilized to achieve the optimal I/O density. Meanwhile, memory devices have traditionally used wirebond interconnect to enable connections to the center row of pads as well as the exterior of the die. Stacked memory packaging has driven a different approach in the industry that provides for the highest memory density and mix of memory capabilities in the same package.
So, to integrate RF, analog, memory, and digital cores onto a single IC, is there one package technology that meets all of these needs? And, if so, at what cost, and how can we best optimize our IC and package technologies for this level of integration?
CMOS Digital ICs are typically packaged in Ball Grid Array (BGA) packages. As pin counts increase and die sizes decrease with finer lithography wafer technologies the trend to finer and finer ball pitches are being realized. Today's products are moving from 1.2 to 1.0 to 0.8 to 0.5mm array pitch to prov ide for the best cost / density trade-offs. One might think that an SoC approach would simplify packaging with the promise of lower total system pin counts as more interfaces are integrated on the chip or within the package. However, the contrary is being seen. As more features are being added and die sizes are shrinking, we are finding fewer pins in a system, but a much higher pin density on a few devices.
Although new pc board and assembly related technologies, such as via in pad, laser vias, stacked die packaging, and fine w/b pitch are being introduced to try and solve the increasing I/O density challenges, many carry an unacceptable cost premium for users.
For BGA pin counts greater than 500 I/O the interconnect density from the die to the substrate is driving high end ICs towards flip chip interconnection. Traditionally, IC suppliers have avoided flip chip interconnect due to the premium substrates required and higher total cost of the solution. With increased I/O density, the co st per unit area increase encountered in the higher density substrates can be off-set by a smaller more dense footprint that is realizable for a flip chip interconnected BGA.
In some cases, flip chip interconnections can also be driven by the electrical requirements for the device. Flip chip interconnect offers lower inductance I/O, better power / ground distribution, and the flexibility to connect directly from the package to anywhere on the die. The drawback to flip chip interconnection is that most flip chip designs require at least a 4 layer substrate (often 6 layers) with finer lithography and via geometries for routing, whereas wirebond designs for the most part are able to utilize lower cost 2 layer substrates.
Thus, whether using flip chip or wire bond one must make the decision based on both cost and performance considerations. If the performance of a wirebond solution is adequate then one does not need to venture into a higher cost technology. For some high end microprocessors the electrical performance and I/O densities can not be easily realized with wirebond based solutions. In this case (typically when the I/O counts are > 500 I/O) the designers may lean toward flip chip solely for the performance reasons described.
Memory packages have long used low cost lead frame packages, such as TSOPs or TQFPs. These leadframe based packages accommodated the multi row wirebonds commonly found in DRAM and SRAM Ics and until recently the relatively low I/O counts ( <64). As memory usage has exploded based on recent PC and wireless memory hungry applications, the packaging technologies have evolved as well.
For higher pin counts and higher pin count densities the memory market has also moved to BGA format packaging. One of the significant advantages sited by the memory suppliers in moving to BGA (or FBGA, Fine Pitch (0.8mm) BGAs) has been that the package footprint is retained as the memory die are shrunk from generation to generation. T his is an attractive feature for customers who do not want to re-spin their product boards to take advantage of the die and cost reductions that drive the memory market.
Stacked die packages are an exciting area of packaging that has been driven by the need for both higher memory density and the combination of different memory types (a variety of Flash + RAM configurations are available). The ability to stack 2, 3, 4 or even more die in a single package and utilize wirebond interconnection to the package substrate significantly reduce the amount of board area consumed by the memory subsystem as well as the routing congestion and many of the EMI concerns of the users.
In addition, many companies claim that a stacked packages cost is significantly less than the cost of the two packages that it replaces. The combination of cost and board savings along with the added flexibility has fueled a large growth in this area over the past several years. Research into extending this approach toward 3D integration has spawned a number of start up companies and led to new thinking in the industry beyond even memory die stacking.
The possibility of combining different functions and technologies and integrating them vertically has extended to combining Baseband processors and memories as well as other heterogenous IC functions. System- in- Package (SIP) integrations such as a stacked die package has enabled higher levels of integration and density than is realizable for today's SOC based approaches.
Packaging of RF components and transceivers has been accomplished in relatively low lead count lead frame based packages such as TSOPs and QFPs. The major requirements for RF components were small size, low inductance I/O and solid ground contacts. As pin counts and complexities have increased over the past few years the packages available have become more diverse.
To many, today's RF single chip package of choice is the QFN or MLF package, which is similar in construction to the QFP package, but has a near chip scale package approach, by minimizing the lead frames length and providing good performance. In general, RF devices try to utilize leadframe based approaches and avoid substrates to minimize costs. As long as the I/O density remains low (<48) this appears to be the most effective solution.
Packaging for analog ICs have covered the area between low to moderate I/O counts. Many of the low pin count analog Ics utilize lead frame package technologies, similar to those used for RF IC packages. For the higher pin count analog devices, the requirements have driven them to utilize substrate based BGA packages. As some analog circuits can be sensitive to noise, careful consideration of the package design must be taken. The integration of analog and baseband functions has been implemented in BGA packages by carrying the noise considerations forward and floor planning the ICs and substrates to avoid coupling into the sensitive analog nodes.
Modules or SIP (Syste m- in- a- Package) solutions have also become more popular as an alternative approach to reduce size, part count, ease of use, and cost to SoC based solutions. For RF applications, where controlled impedances, multiple IC technologies and a great deal of SMD (Surface Mount Devices) are present SIP based solutions are favored by many. This is especially true for Power Amplifier or Front End Modules (FEMs) in wireless applications where SoC integration has not been easily realized, due to the high power, voltage and low loss requirements. Relative to IC packages, these modules come at a higher cost premium as measured in cost / pin or cost / mm2.
SoC, SIP coexistence
The key for SIP integration to be successful is that the solution size, parts count, and electrical losses are significantly reduced with this implementation. When the total implementation cost realized with a modular approach is lower than with an SoC approach, as is the case for many of the wireless and especially cellu lar- based FEM applications today, then the module based solution will be utilized.
Therefore, as many experts have stated in conferences and in articles, the coexistence of both SoC and SIP approaches is foreseen.
Packaging considerations play a vital role in the architectural decisions made when bringing any system together. As SoCs become larger and more functions are integrated into a single package, early consideration must be given to total pin count for any particular IC, routability of the pc board on which the IC will be placed, electrical performance of the package, noise, isolation, thermal dissipation capability and of course cost. Careful consideration of these items will allow the system architect to simplify the design, minimize risks, ease validation and minimize cost. Packaging can be utilized as an advantage in many cases to limit bandwidth, provide needed inductance or isolate circuits.
Many of these concerns are most relevant when considering mixed signal systems where there are analog circuits on the same IC as a large complex digital ones. In this case, providing an architectural partitioning that allows higher and higher levels of integration while minimizing the risks and cost is critical. This may include only integrating those circuits which are less susceptible to noise, have limited frequency range requirements and will be cost competitive in the SoC technology.
Significant SoC packaging challenges exist for further integration of a variety of functions. In some cases packaging will cause problems that must be overcome. For example, integrating a significant amount of power management onto a very high I/O count BGA will present problems with thermal dissipation. On the other hand, creative packaging configurations can also be used to solve problems.
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