Systems-on-programmable chips: A look at the packaging challenges
Systems-on-programmable chips: A look at the packaging challenges
By Tarun Verma, Director of Package Technology, Martin S. Won, Senior Member of Technical Staff , Altera Corp., San Jose, Calif., email@example.com, EE Times
May 23, 2003 (10:00 a.m. EST)
Complex FPGAs are increasingly taking on the characteristics of complete systems-on-a-chip, including embedded memory and processors, specialized I/O, and multiple differentiated power and ground planes. Developing packages for these devices presents a set of challenges both common to other SoC offerings and unique to systems-on-programmable chips (SoPCs).
For example, programmable logic device (PLD) vendors offer their customers the ability to develop and verify designs for their devices well before the actual devices are shipped which is typically 4-6 months before first samples are available. This necessitates the packaging aspects of the entire product family to be finalized before that. These aspects include items like pinout and electrical and thermal characteristics which collectively facilitate early board layout, design timing and verification, signal integrity analysis, and power budgeting.
Programmable logic vendors als o offer customers the ability to migrate designs between different device family members with the same package and pinout avoiding expensive board re-spins. This feature is called vertical migration and has been largely accomplished through the package/die layout optimization. Facilitating this capability has required proactive development of associated substrate technologies to support the routing densities required.
Altera has been one of the early users of high-density interconnect (HDI) technology and has and continues to work extensively with these providers to enhance capabilities and improve performance. One of the more recent challenges in programmable logic packaging has been the integration of high-speed transceivers.
The proper operation of these transceivers requires several extra demands on the packaging of these devices, including equalizing trace pair lengths to minimize skew and optimizing transmission line impedance. The deleterious effects of small discontinuities become increasingly evident at these data rates, in excess of 3.125 Gbit/seconds. In addition, signal integrity should be maximized by optimal trace placement and an overall reduction of inductance within the package, in particular from the multiple power and ground planes that are required to support device operation. All of these factors are interdependent, and slight changes to influence one of them can cause unforeseen changes in others.
Such requirements necessitate silicon package co-planning and design. Considerations are made for silicon-package partitioning and package power optimization at the product planning stages. This analysis is done using comprehensive simulations to determine package characteristics many months before actual packaged units are available. The entire packaging design is now an integrated, iterative process involving optimization between pin layout, chip layout and cost performance objectives. This has been significant change in packaging design methodology which has be en quietly evolving over the last four to five years.
Altera's experience with its first generation of transceiver devices the Mercury FPGA family, enabled us to establish procedures for the complex simulation of transceiver-based FPGAs, laying the groundwork for its more recent work with the Stratix GX family. At that time, Altera package engineers discovered that they had to develop a common framework and process to address both the mechanical and electric aspects of these increasingly complex packages.
Working with the silicon design engineering team and using a combination of tools from multiple vendors, the package engineers were able to develop accurate models of the electrical behavior of the packaging circuitry that, when used with the IC design test bench, would indicate the overall behavior of the packaged die on the board. These models included ball-to-transmission line, transmission line, and transmission line-to-bump H-spice models, as well as S-parameter model s of the ball-to-bump behavior.
This process enabled Altera's engineers to accurately predict the signal integrity behavior of the Stratix GX device several months before actual silicon was available.
The increased emphasis on signal integrity is coupled with enhanced customer usability requirements of managing power dissipation and board mounting considerations such as accommodating various reflow conditions for different package lead finishes. The implementation of lead-free packages adds an additional flavor to these challenges.
Our approach to these challenges has been to develop modeling techniques using finite element methodologies to allow them to predict board-level behavior. Typical customer requirements are for 2000-5000 cycles of board-level reliability through 0-100°C, with slight variations such as higher temperature requirements or greater number of cycles for certain market segments, like communications, industrial, consumer and automoti ve.
Programmable logic devices tend to be high pin count with relatively large die sizes. Component and board-level reliability are realized by starting with optimal silicon and package design. Programmable logic vendors need to partner closely with their assembly partners to optimize processes to meet customer requirements of reliability and manufacturability. This includes participation in the material selection for substrates/leadframes, underfill and die attach as well as encapsulation. Modeling as well as empirical techniques are used to validate these using test vehicles prior to product introduction.
Going forward, recent advances in semiconductor processes like the transition to 300 mm wafers or the introduction of low-k dielectric materials are also impacting package technology. For example, low-K dielectric materials are more brittle than conventional FSG dielectrics, and package engineers must determine ways of maintaining high reliability in the face of this differe nce. These methods might include developing design rules that influence the use of low-K dielectrics during IC layout, or identifying an appropriate bill of materials to meet the customer requirements. The enhanced power dissipation that is anticipated at the 90 nm node will also influence packaging choices for next-generation devices.
As devices continue to progress towards higher levels of integration, the packaging aspects are becoming a part of product feature set. The associated methodologies and processes need to evolve to keep ahead of the curve. The concept of system-level designs with co-design and co-optimization of the various subsystems is gaining momentum in the industry. Semiconductor vendors are facing these challenges need to continue working as enablers, drawing upon several technologies to advance the state of the packaging art. An increasing amount of participative effort of the EDA, foundry and silicon engineering community along with the packaging community is needed to support these needs.
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