Nanometer SoC complexities require more work in silicon, package co-design
Nanometer SoC complexities require more work in silicon, package co-design
By Stan Mihelcic, Senior Marketing Manager, Lucas Tsai, Senior Marketing Manager, Advanced Silicon Solutions, LSI Logic Corp., Milpitas, Calif., email@example.com, EE Times
May 23, 2003 (9:55 a.m. EST)
As the semiconductor industry drives into nanometer silicon technologies, the race to keep up with Moore's Law has hit some stumbling blocks. Since the introduction of SoC design methodologies in the mid '90's, silicon and packaging technologies have been pushed to support higher performance, lower power, finer geometries and denser I/O solutions.
The advent of the 130nm silicon node introduced the use of copper metallization and low k dielectrics, promising faster performance, smaller chip sizes and lower power consumption. As the industry struggles with the reliability of silicon designs using copper/low K ('true' low K =<3.0), a more recent problem with respect to the packaging interaction with the silicon chip has emerged. The mechanical properties of both silicon and package need to be characterized to ensure the mechanical integrity of the finished product is not compromised. To achieve this, the combination of silicon and package must be co-developed to ensure a total solution can be manufactured with reliable performance.
It has been predicted since early 90's that the interconnect RC delay would dominate chip performance as the silicon industry ventured deeper into the Moore's Law. The crossover point where interconnect RC delay surpassed gate level delay occurred earlier for cell-based ASIC design through logic synthesis as opposed to full-custom microprocessors where the logic gates are crafted for optimal loading and placed in more compact manners.
Leading ASIC companies responded to the challenge by rolling out novel materials in metal stacks. This was evidenced in the 0.18mm node, in which IBM implemented copper metallization and LSI Logic offered low K inter-metal dielectric (IMD). Meanwhile Intel did not use Copper or any low K material until 0.13 mm node.
When introduced to ASIC design community, copper metallization along side low K IMD was considered at the 0.13mm technology node.
However, a co uple of then unexpected but now well-documented integration difficulties significantly challenged the deployment of new materials, particularly low K IMD with K < 3.0. IBM's formal foundry partner, UMC, announced early in 2002 that they were abandoning the existing low K strategy, which used a spin-on material SiLK. UMC switched back to a more stable, but higher K value FSG (Fluorinated Silicate Glass), and soon IBM followed suit. On the contrary, LSI Logic provided knowledge and experience in 0.18mm low K production to alliance with foundry partner TSMC, successfully overcoming the integration challenges with copper metallization. The result of the TSMC/LSI Logic collaborative effort is production libraries and IP portfolio based on true low K (K=2.9) IMD process platform, which leveraged Applied Materials' Chemical Vapor Deposition (CVD) process, a material called Black Diamond.
We need to be careful where to implement low K, and where not to, since the superior electrical performance of low K IMD comes at the expense of inferior mechanical and thermal characteristics. In LSI Logic's 0.11µm ASIC technologies, Gflx, low K IMD are only implemented at the bottom dense signal routing layers, where most of the signal routing wires reside. The top three metal layers with larger metal pitch are used mostly for power mesh, and low resistance is more important than lower wire-to-wire capacitance, as can be witnessed by a much thicker Cu metal. Also, since these layers are closer to the passivation layer and bonding pads or flip chip bumping layer, where the stress level is usually the most significant and critical, regular SiO2 instead of low K IMD was used.
For example, when using eight layers of Cu metal interconnect, only the bottom 5 layers contain low K IMD. The thick metal significantly extends the current carrying capability of the power mesh to avoid voltage droop issue. SiO2 IMD in the top layers, provides excellent stress buffer, and significantly relieve the concerns on both bonding or bumping damage and assembly yield fall-off.
Plug n' play no more
Packaging technology has traditionally been taken for granted, as a 'plug and play' component for the silicon chip design. In the past decade, packaging technology has taken a greater role in determining how systems are partitioned and how chip designs are architected. With SoC design methodology, whole systems have been integrated into single chip solutions. The level of integration has created new demands for packaging technology. I/O counts have increased from the low hundreds in the early '90's to the few thousands today. Electrical performance of the chip design requires packaging technology to support signaling speeds into the GHz spectrum.
To develop a successful SoC design, the package must be part of the design cycle from the very beginning. Whether the design uses flip chip packaging technology or wire bond interconnect, floor planning the SoC design will be impacted by the packaging technology chosen. p>
As the industry was concentrating on developing copper metallization and low K dielectrics silicon processes, package technology was not considered part of the development cycle. Today, several companies have struggled not only with the silicon process part of the development but also the package and it's interaction with the silicon device. To understand the complications of Cu/low K packaging, we must first understand the basic reliability concerns with non Cu/low K devices.
Flip chip packaging technology utilizes very small solder spheres, also known as solder bumps. These bumps are part of the silicon chip. The silicon chip with bumps is mounted to the package substrate, similar in operation to a surface mount board assembly process.
When using ceramic substrates, the interconnect reliability of die to package is relatively good. If an organic (plastic) pac kage substrate is utilized, additional steps are required to ensure a reliable interconnect. This is primarily due to the difference in the Coefficient of Thermal Expansion (CTE) between the silicon chip and the package substrate. The CTE of silicon is approximately 2.6 ppm/°C. Organic substrate technology's (BT resin and PTFE) have greater mismatch compared to ceramic materials.
The CTE mismatch between the silicon and the substrate produces a bending or curvature of the assembly and thus the silicon die upon changes of temperature. This type of thermal/mechanical stress can lead to solder bump fatigue. To overcome the problems associated with silicon/package CTE mismatch, a compliant underfill material (typically epoxy/resin) is dispensed between the silicon die and the organic package. The underfill material provides stress relief to both silicon and substrate ensuring the mechanical integrity the assembled device is not compromised. Over the past ten years, a tremendous amo unt of work has been done to develop and characterize underfills, which provide the mechanical stability required of the organic substrate.
Organic packaging technology has become pervasive due to its excellent electrical properties and its relative low cost compared to ceramic technologies thus making it the package technology of choice for most applications. Today, organic flip chip package devices are produced in the millions for various applications including: ASIC/SoC, microprocessors and graphics chip sets.
With the introduction of Cu/low K silicon processes, new concerns developed. As explained earlier, due to the mechanical sensitivity of the low K material, stresses induced by the package has been demonstrated to exasperate the problem. Delamination of the low K material from the metal stack and cracking in the low K material are the primary areas of concern.
Although underfill materials were successfully developed over the past decade, the introduction of Cu/low K silicon pr ocesses requires additional research in the areas of low stress underfills and assembly processes optimized for Cu/low k silicon.
The initial step in developing a Cu/low K compatible flip chip package is to model the physical interaction between silicon and package. Components of the package construction are identified along with their material properties. Once the model is created, simulations of the package assembly process are carried out to measure the stress effects on the silicon die. Mechanical stress modeling and simulations have been proven to greatly reduce the overall development cycle and reduce costs associated with long term environmental stress testing.
Results from mechanical stress modeling provided critical feedback to both silicon process engineering and package development groups. Upon completion of stress modeling simulations, reliability evaluations were performed on devices assembled. In addition to achieving successful results, data from str ess modeling and reliability testing achieved correlatation. Reliability evaluations of the newly optimized package have led to the qualification of flip chip packaging technology using Cu/low K silicon.
As done with flip chip packaging, wire bond packaging also has to be closely evaluated to ensure the package material system does not induce stress to the Cu/low K silicon structure.
The main components of the wire bond package material system include substrate (in this case, organic), die attach and mold compound.
Wire bond packaging is also susceptible to the CTE mismatch of the silicon die and the organic substrate. Although failure modes attributed to CTE mismatch in wire bond are not as pronounced as they are in flip chip packaging, stress modeling and simulations are required to understand the interaction of the material set to the Cu/low K silicon. The mold compound is identified as the primary contributor to die stress.
Wire bond packaging is challenged to support ev er shrinking die sizes and electrical performance demands. A novel wire bond approach has been introduced by LSI Logic named Pad on I/OTM. Traditionally, the wire bond pad ring is placed on the outside edge of the die. In addition to the bond pads consuming silicon area, I/O slots on the die are required to support Vdd and Vss connections. The new Pad on I/OTM approach eliminates the need to grow the die to support physical pad structures by flipping the pads on top of the active I/O structures. Dedicated bond pads are connected directly to power and ground busses in the die removing the needed for dedicated I/O slots to support package Vdd and Vss. The result of Pad on I/OTM is signal density comparable to flip chip and improved electrical performance.
In addition to the complications of material interactions of the package material set and Cu/low k die, wire bonding on top o f active circuits must be characterized to ensure the structural integrity of the die is not compromised. Co-development of Pad on I/OTM between silicon process, circuit design and package development was carried out to develop this capability. The silicon pad structures and underlying metallization layers were designed to support the mechanical stresses induced by the wire bonding process.
The result of this development is wire bond technology utilizing Pad on I/OTM , compatible with Cu/low k silicon in a production assembly environment.
Complexities of nanometer SoC design require the co-design and development of silicon process, circuit design and packaging technology to enable a successful 'total solution'. The physical interaction of silicon and package requires close attention, especially as packaging materials change and silicon processes introduce even lower K materials.
Copyright © 2003 CMP Media, LLC | Privacy Statement