Design rules push SoC packaging to the forefront
Design rules push SoC packaging to the forefront
By Mike Clendenin, EE Times
June 3, 2003 (1:31 p.m. EST)
The rise of system-on-chip devices, along with the challenge of 130nm design rules and the looming challenge of 90nm design rules has, and will continue to, test old methodologies and, more often than not, force them into retirement. Those who doubt this change probably won't be working in the industry must longer.
Conversion to the new paradigm need not be so bad, though. Chip designers will get to know, more collegially, a whole new set of colleagues those "package guys" who until recently, were the unheralded workers who stitched together the covering for your Ferrari. With SoCs, those package guys are now designing their own hifalutin' rides.
In an exclusive online piece, LSI Logic Corp.'s Stan Mihelcic and Lucas Tsai, argue quite effectively that packaging technology should no longer be taken for granted as a "plug-and-play" component. "The level of (SoC) integration has created new demands for packaging technolo gy," they note. " I/O counts have increased from the low hundreds in the early 90's to the few thousands today. Electrical performance of the chip design requires packaging technology to support signaling speeds into the GHz spectrum. To develop a successful SoC design, the package must be part of the design cycle from the very beginning."
This sets the stage for a number of contributions to this week's In Focus from engineers at Altera Corp., STAmericas, Texas Instruments, Motorola and NEC Electronics. In this SoC era, each of these companies has made conceptual adjustments to their design methodologies. And, all, it seems, are waiting for the EDA industry to follow with tools that will help standardize and thus institutionalize this change. Such tools will undoubtedly make simulating package effects on a system much easier and more accurate.
"The development of package co-design methods and tools is ongoing," say co-authors Gary Morrison, Vinu Yamunan and Adelina Lewis of Texas Instrument s. They point out in their contribution, that "although we might not be to the point that we have comprehensive, user-friendly, and tightly integrated tools that seamlessly span all design environments existing package co-design tools, with the right methodology and custom-developed internal tools, will provide crucial benefits."
And, they point out that today's tools have already reduced design cycle time from days to hours. Their article provides a few brief, but helpful case scenarios.
Meanwhile, Altera's Tarun Verma and Martin Won note that the ability to accurately simulate package effects is especially important for programmable logic device (PLD) vendors. Often, at least six months in advance of samples, their customers need to verify parameters such as pinout and electrical and thermal characteristics which collectively facilitate early board layout, design timing and verification, signal integrity analysis, and power budgeting, they say.
Pointing out the recent integration of high-speed transceivers into PLDs, their advice is that early collaboration is even more important. "The proper operation of these transceivers requires several extra demands on the packaging of these devices, including equalizing trace pair lengths to minimize skew and optimizing transmission line impedance," they write. "The deleterious effects of small discontinuities become increasingly evident at these data rates, in excess of 3.125 Gbits/second."
Verma and Won also note that the change in packaging methodology toward a collaborative approach has been "quietly evolving" over the past four to five years. "The entire packaging design is now an integrated, iterative process involving optimization between pin layout, chip layout and cost performance objectives. Considerations are made for silicon-package partitioning and package power optimization at the product planning stages."
And contributors from STAmericas and NEC go beyond the package to the printed circuit boa rd, in an attempt to assess the impact of chip- and package-level decisions on downstream performance.
Engineers, Tomoaki Isozaki and Hirofumi Nakajima at NEC describe a "virtual board" design. and lay out a detailed design flow from chip to board, describing various considerations, such as the interposer material and the limitations of system-wide modeling. Tools are also cited as a concern.
They note that "although there are commercially available individual EDA tools for each component, SoC designers have experienced the lack of interaction between these tools, or verification of the accuracy of simulated data. Full interaction of each of the component models and verification of the simulated data are the driving force to a balanced design between electrical and cost performance in a short lead-time, which is the final goal of our co-design framework."
Mike Hundt and Rich Evans from STAmericas also explore the pc board especially in small form-factor applications, and its influence on upstream components. They point out that the usual pecking order has been reversed. "Limitations and requirements set at the pc board level now feed back through the package (defining the package on the way) to the IC, where they can define a significant portion of the IC's design. Those who fail to see and accept this reversal do so at their peril," they say.
The articles for the In Focus report on packaging SoCs can be found here.
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