Certifying RISC-V: Industry Moves to Achieve RISC-V Core Quality

By Dave Kelf, Breker Verification Systems
EETimes (June 11, 2024)

The board of RISC-V International has launched a certification committee to address the need for a provable quality benchmark for RISC-V.

At the RISC-V Summit North America in November 2023, Simon Davidmann, CEO of Imperas (now Synopsys), delivered a surprising keynote. His message: While RISC-V was an enormous leap forward, the limited focus on quality could ultimately kill the initiative. This was a view shared by many stakeholders.

Davidmann went on to explain that a quality expectation had been set across the semiconductor industry by companies like Arm and Intel. Bugs in their processors have been extremely rare, and users rely on that quality level, as a processor bug could kill an end product. Davidmann noted that Arm spends more than US$150 million on verification annually, runs a staggering 1015 (greater than the number of miles in a light year) verification clock cycles per core and has 30 years of experience under its belt. This is made easier by retaining complete control of the instruction set.

RISC-V users expect this “Arm quality” level, because without it, their designs will fail. But how can RISC-V core providers hope to meet this quality goal, and how can they prove it?

RISC-V: new processor thinking

Before the advent of RISC-V, most processor instruction set architectures (ISAs)—the fundamental code specifications used to drive the device—were the protected intellectual property of the company that developed the processor. This protection was critical to the company, as it allowed ecosystem control and blocked competition, enabling favorable business models.

Along came the RISC-V open ISA. Any company could use the instruction set for its processor implementation, software stack, tools and other ecosystem elements. Business models would no longer be dictated by the ISA copyright. In addition, the RISC-V ISA was more flexible than others, allowing the inclusion of differentiating custom instructions.

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