Panel sorts out reality of 130 nm design

Panel sorts out reality of 130 nm design
By Ron Wilson, EE Times
June 4, 2003 (3:03 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030604S0031

ANAHEIM, Calif. — How does a chip design team manage to get from their existing knowledge base to a successful 130 nm design? Is it turnkey, or complicated, or simply impossible for all but a privileged few teams? A panel representing the foundry, library and EDA businesses attacked that question with gusto at a lunchtime session here at DAC on Tuesday (June 3).

Scott Becker, CTO and co-founder of Artisan Components, Joe Sawicki, vice president and general manager of the Design-to-Silicon group at Mentor Graphics, and Kurt Wolf, director of library management at Taiwan Semiconductor Manufacturing Corp. (TSMC) took on the issue. But as one member of the audience observed, the three spoke more as component members of a design chain than as competitors with conflicting interests.

Becker outlined the well-discussed challenges facing designers of 130 nm chips, including complexity of the design itself and the rapid intrusion of physics and retic le enhancement technologies into the mix. He also listed some of the well-understood solutions to these issues, including new point tools and greater control over the power and voltage environments.

He suggested that many of the necessary techniques, though in themselves complex, could be encapsulated in IP, such as libraries, to present reasonably workable models to the design team.

Sawicki focused on back-end design in particular, discussing the spiraling of design rules to nearly 600 in 90 nm processes and the massive growth in feature counts on masks. He suggested that the interface between the design team and the process still existed at the design rule checking (DRC) stage, and that much of the process complexity was being absorbed into the rules along with the tools that checked the database against them.

He cited the evolution in DRC tools from the days of a long, silent run followed by a ''a smiley face or a frowny face.'' Today, he said, the DRC stage is likely to not only list rule vio lations, but to insert enormous amounts of additional data into the polygon files to handle OPC or phase shift features.

In the future, he suggested, the DRC tools would also in effect engage the user in a conversation about recommended-rule violations, manufacturability guidelines and potential optimizations.

Wolf agreed in part on the growing role of DRC, but also emphasized that much of what foundries learn about the use of their processes is captured in checkers and scripts that accompany the process design kit. Some steps, such as inserting widened or doubled vias to account for via formation issues, would have to be implemented as tools, Wolf suggested, but this should be back-end work that for now would be invisible to most design teams.

Other issues, such as inserting low-voltage, low-leakage or high-speed specialized cells from highly flexible libraries, should be done explicitly during or just after placement.

The panel ultimately agreed that, as 130 nm designs proceed toward tape- out, that event looks less like a hand off and more like a joint development project. Successful 130 nm designs, they said, are the result of careful collaboration between foundry, tool and IP vendors and design team. They are not a result of picking up the design kit, purchasing the right libraries and licensing the right tools.

They said information must be shared in all directions, including between IP vendors such as Artisa, who have been through the process flow before, and design team or even other IP vendors.

IP vendor is critical

The panel also agreed that choice of IP vendors was critical since successful IP development was as much the result of a collaboration with the foundry as was successful chip development.

Looking forward to 90 nm and 65 nm designs, the panelists said collaboration will grow, with no walls springing up to shield design teams from increasing process complexity. In fact, they cited a number of process-related issues that would have to be moved further forward in the design flow rather than isolated in the mask-making or DRC phases.

While admitting that 130 nm design was difficult, Wolf said tens of thousands of wafers have shipped from TSMC at 130 nm. It's not easy, but with design team, foundry, library and tool vendors working together the collaboration can work, said.