Test may decide choice of SoC or system-in-package

Integration at the chip level, such as in SoCs, results in a much larger die in comparison with the individual dice in SiPs; this is why SoCs provide a relatively low yield. According to the International Technology Roadmap for Semiconductors' yield calculator, the introductory test yield in 90-nanometer technology for 100 mm2 dice would be 46 percent, for 200 mm2 dice 23 percent and for 400 mm2 dice 12 percent. Thus, an SiP with four to five 100-mm2 dice can still be feasible, but a single 20 x 20-mm SoC die is out of the question. The problems of yield and test time increase geometrically with the increasing die size. Therefore, the total problem-space in a system containing multiple small dice is much smaller than the problem-space of a single, large SoC.

The key manufacturing step in SiP is that all small dice must be "known good." Scrapping an SiP means scrapping five to 10 good dice that have gone through all the tests along with a defective die. Therefore, the cost of even the smallest scrap is too high.

Hence, from a testing point of view, wafer-level testing to determine known-good dice is not adequate for SiP. The defects in wafer saw, die attach and wire bonding result in expensive scrapping in the SiP manufacturing process. This places a new demand on the test process.

Last year, Advantest announced a new test system based on patented technology that can potentially solve this problem. CertiMAX works in the event environment. That is, instead of a conventional test program, the system uses design-simulation data directly from the Verilog/VHDL simulator in VCD format. Thus, this test system can quickly determine if every individual die is functionally correct when intended for use in an SiP. Similarly, a quick SiP-level functional test also can be run on CertiMAX. Since all individual dice are filtered just prior to the die-attach and wire-bonding stages, the SiP gets "real" known-good dice. This results in a significant reduction in scrap and overall cost.

SiP test also requires test reuse and that each tester pin operate independently. While the per-pin architecture of CertiMAX permits concurrent testing of individual IP cores in an SoC, it also provides efficiency and cost-effectiveness in the SiP test. The event-driven format also allows straightforward programming in the testing of die-to-die connections in SiPs. With such an approach, SiPs are likely to become a real contender and a promising alternative to SoCs for certain applications.

Rochit Rajsuman is chief scientist at Advantest America R&D Center (S anta Clara, Calif.).

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