NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
A white paper written by Electra IC Team; Merve Eyüboğlu, Murat Tökez, Ibrahim Mouamar Ali Ahmed, Melike Atay Karabalkan, and Berna Ors.
Electra IC Advanced Verification Suite (EAVS) for RISC-V Cores is a powerful and flexible RISC-V core verification environment. It integrates a UVM testbench, Instruction Set Simulator (ISS), and automated validation tools to ensure compliance with RISC-V standards.
With randomized test generation, parametric flexibility, and seamless core integration, EAVS-DV enhances verification efficiency and accelerates development. Designed for adaptability, it supports various RISC-V implementations, providing a scalable and reusable solution for next-generation processor validation.
To read the paper, click here.
|
ElectraIC Hot IP
Related Articles
- Certifying RISC-V: Industry Moves to Achieve RISC-V Core Quality
- Hardware-Assisted Verification: Ideal Foundation for RISC-V Adoption
- A formal-based approach for efficient RISC-V processor verification
- Maven Silicon's RISC-V Processor IP Verification Flow
- A closer look at security verification for RISC-V processors
New Articles
- Optimizing 16-Bit Unsigned Multipliers with Reversible Logic Gates for an Enhanced Performance
- How NoC architecture solves MCU design challenges
- Automating Hardware-Software Consistency in Complex SoCs
- Beyond Limits: Unleashing the 10.7 Gbps LPDDR5X Subsystem
- How to Design Secure SoCs: Essential Security Features for Digital Designers
Most Popular
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |