Timing key to optimizing audio performance in consumer products

The loss in a system's dynamic range is due to the increase in the noise floor. A high noise floor can cause a hissing sound when played back over the system speakers. Background hiss is most apparent during a quiet movie scene or a soft passage in a classical music recording. And audio captured with a system with inadequate dynamic range will always sound inferior.

Increasing dynamic range for greater audio signal reproduction and reducing annoying background hiss are only a couple of reasons to look at clock design. Many consumers today look for a certain level of performance and compatibility in the A/V products they purchase.

Two insignias these consumers are especially interested in are the Dolby Digital and THX conformance logos. These logos promise a minimum level of audio performance and compatibility. But poor audio performance can prevent a product from passing the Dolby Digital or THX certification tests required by their respective companies.

With so much riding on audio performance and good clock design being key to good audio performance, it's important to know the design issues affecting clock accuracy and jitter.

These issues begin with the audio converter master clock. In a typical DVD receiver design the video clock is based on a crystal oscillator and, in order to maintain proper decoding between the audio and video, the audio clock is synthesized from the video clock using a PLL. The flexibility of the PLL is also used in generating the correct audio converter clock frequencies as the audio stream content changes, for example, from 48kHz audio for DVD to 44.1kHz for CD playback. The clock synthesized from the PLL becomes the only source for generating the audio clocks.

To save costs many chip companies integrate the PLL into the DVD processor. However, due to inadequate chip layout, high-frequency switching noise, or poor isolation of power-supply rails the output of the PLL can contain a considerable amount of wide- band jitter. Even though most PLLs are designed using a lot of digital logic, they are fundamentally analog systems. This means that a low-jitter PLL does not co-exist well on an otherwise digital chip. Good PLL design is a mixed-signal technology and requires design methodologies used by accomplished mixed-signal designers.

The PLL-generated master clock is then distributed among discrete components such as the digital to analog converters used for playback, analog to digital converters used for audio capture, and the S/PDIF Receiver used for the digital interface. Understanding and compensating for these signal loads and the associated board routing are critical to maintaining the integrity of the high-speed master clock. Impedance matching and transmission line effects must now to be considered in order to reduce possible reflections of the clock edges.

Companies use various strategies to address poor clock performance. For low cost products, a manufacturer may only marginally pass the requirements established by Dolby, while allowing poorer performance on audio source material from analog sources and digital audio from CD's and PCM from a digital interface such as S/PDIF. This approach may make sense where cost outweighs quality audio.

For mid-range A/V products where Dolby and THX certification is important, as well as overall audio performance, some designers choose to use higher resolution DACs and ADCs (which may also advertise less sensitivity to clock jitter) to increase dynamic range.

In this case the hope is that the greater design margin will overcome performance degradation due to clock jitter. But higher resolution DACs and ADCs cost more and may also require additional power supply filtering and op amp buffering. A/V products using these techniques have been carefully designed to reduce the sources of clock jitter, increasing design time and board complexity. Another technique is to implement a high-quality PLL off-chip using discrete components. Ad ditional card logic will be required, which not only increases system cost but also can be a source of clock jitter itself.

Using the right clock

A single master clock source for each audio source is not always the best solution. In the case of a DVD receiver, for example, there are typically three sources of audio. One source is analog audio from a VCR, camcorder, or TV. These sources are converted to digital audio and post-processed for features such as Dolby Pro Logic/Pro Logic II and bass management. Since no video synchronization is required for these sources the best clock to use in this case is an oscillator. A quality oscillator is considered the optimal source for a low-jitter clock.

Another source of audio content is an S/PDIF digital interface providing either PCM or compressed AC3 multi-channel audio. Typical examples include CD players, satellite receivers, or set-top boxes. Digital audio from an S/PDIF interface can also be post-processed for fe atures such as Dolby Digital/Pro Logic/Pro Logic II, DTS and bass management. For proper data extraction, a PLL is used to lock onto the imbedded clocking information and recover the clock from the incoming S/PDIF data stream. The recovered output clock of the PLL is used as the master clock for all DACs and ADCs in the system.

A third audio source in a DVD receiver is digital audio samples from a CD/DVD audio disk, or compressed audio and video from a DVD disk or an IEEE-1394 interface. The best choice in this situation is a high-performance, low-jitter PLL.

Ideally, a DVD receiver should utilize the clock most appropriate for the audio source the user has selected. One way of doing this is to use a new generation of integrated audio codec chips such as the Cirrus Logic CS42528. This new codec has the highest level of part integration to support common consumer electronic functions such as 2 channels of ADC, 6 or 8 channels of DAC, and an S/PDIF Receiver, all capable of supporting up to 19 2kHz sample rates. In a typical DVD receiver design the CS42528 is partnered with a DVD processor such as the Cirrus Logic CS98200.

For analog audio sources (TV, VCR, CD player) a 12.288-MHz oscillator connected to the OMCK pin of the CS42528 provides the low jitter audio master clock used by the internal DACs and ADCs. The RMCK clock output pin can be configured to supply this audio master clock signal to the CS98200. The CS98200 audio processor and audio serial port must use this clock to operate synchronously with the output data rate of the ADCs. Following the post processing algorithms, the audio data samples are sent to the DACs in the CS42528 for playback. The audio sample rate is selectable from 32kHz up to 192kHz.

Since the oscillator clock source used by the ADCs and DACs is local to the chip, and all logic and routing are internal to the part and were designed to minimize any potential sources of jitter, optimal performance is achieved.

When a compressed (IEC61937) or P CM (IEC60958) digital audio source connected to the S/PDIF port is selected, the CS42528's integrated PLL recovers the clock from the S/PDIF data stream. The extracted low-jitter clock is used to drive the internal DACs and ADCs and is also available on the RMCK pin of the CS42528. The frequency of the clock on the output of the PLL is 256 times the incoming sample rate. A 48kHz incoming data stream would produce a 12.288MHz audio master clock.

Minimizing interference

The analog, digital and PLL sections of the CS42528 are designed to minimize the interference from digital switching circuits on sensitive analog components. Critical clock management circuitry provides clock edge control and minimizes switching effects. Separate voltage supply pins and proper attention to the grounding structure and return currents minimize sources of jitter on the output of the PLL. The measured typical clock jitter on the output of the PLL is 150 picoseconds (rms).

The DVD processor uses this clock for audio processing and to maintain synchronization with the incoming rate on the S/PDIF digital interface. Following any required decompression and/or post processing algorithms, the audio data samples are sent to the DACs in the CS42528 for playback. Sample rates from 32kHz up to 192kHz are supported for the S/PDIF interface.

Because the actual S/PDIF receiver, PLL, DACs and clock switching circuitry are integrated into a single part, typical concerns of number of loads, board trace lengths, impedance matching, and transmission line effects of high-speed signals are not relevant. The sources of clock jitter within the system are significantly reduced yielding an audio clock capable of producing high quality audio.

The PLL integrated in the DVD processor synthesizes the audio master clock, which typically runs at 12.288 MHz or 24.576 MHz. The jitter generally found on this clock will cause the DAC's dynamic range to degrade and introduce harmonic distortion.

To minimize the effects of the master clock jitter from a DVD processor, the CS42528 codec has a feature that allows the codec's internal PLL to lock to the incoming sample clock, AUDO_LR, from the DVD processor and generate an internal master audio processing clock to the DACs. Typically, the integrated PLL in the codec is used to extract the imbedded clocking information when receiving data from the S/PDIF receiver.

Jitter rejection

The re-use of the integrated low jitter PLL in the CS42528 for the playback of DVD and music CD material is accomplished by selecting the input to the internal PLL to lock onto the incoming frame signal on the SAI_LRCK input. Since the sample rate clock from the DVD Processor, AUDO_LR , is derived from the output clock of the DVD processor's internal PLL containing some amount of jitter, it is expected that the SAI_LRCK signal will also contain jitter. However, since the SAI_LRCK frequency is usually 128, 256 or 512 times smalle r than the frequency of the PLL output clock, the amount of jitter present is insignificant relative to the period of the SAI_LRCK sample clock.

The CS42528's PLL provides very good jitter rejection on the incoming SAI_LRCK signal and will generate a low-jitter output clock.

The PLL internal to the CS42528 can support SAI_LRCK sample rate frequencies of 32, 44.1, 48, 88.2, 96, 176.4 or 192KHz. The AUDO_LR sample rate clock signal connected to SAI_LRCK will be locked to the 27MHz master clock and is input to the PLL internal to the CS42528. With this association, the master audio clock generated internally in the CS42528 will be locked to the system 27MHz master clock and will contain a very low amount of jitter.

Since the PLL and clock switching circuitry are integrated within the codec, and the PLL uses the sample rate clock to produce the converter master clocks, the sources of clock jitter withi n the system are significantly reduced. Using this clocking arrangement and a sample frequency of 48kHz, test results have shown a DAC dynamic range of 108dB with 700ps of wide band jitter on the master clock from the DVD Processor. When the DAC's are clocked directly from the DVD Processor master clock, the dynamic range performance is degraded to 89dB.

By using an integrated audio codec, the best clock for the audio source can be generated and selected. An oscillator-controlled master audio clock is optimal for analog sources. For digital audio from a CD player, set-top box, or satellite receiver an on-chip low-jitter PLL generates the master audio clock from the incoming S/PDIF data stream. And for digital audio data from a CD or DVD audio disk, compressed A/V data from a DVD disc or IEEE-1394 port, the on-chip PLL generates a low-jitter clock based on the sample rate information in the serial audio left/right clock from the DVD processor.