Weidan Li, Staff Engineer, Benjamin Mbouombouo, Manager, Technology Definition & Development, Lucas Tsai, Senior Marketing Manager, Advanced Silicon Solutions, LSI Logic Corp., Milpitas, Calif., email@example.com
Decades of remarkable microelectronic technology development has largely benefited from transistor scaling. The smaller feature size allows both higher chip density and higher transistor performance simultaneously. However, the scaling of the interconnect, the other important part of the chip, has not been as smooth.
With shrinking interconnect size, performance is getting worse. Starting with the 0.25 micron generation, the interconnect delay began to surpass the intrinsic gate delay. As technology steps into the nanometer era, the interconnect predominates almost all aspects of the chip design: performance, power consumption, signal and power integrity. The product of the interconnect resistance and capacitance (RC ) for a typical routing wire has been doubled from the 0.18 micron generation to the 90 nanometer generation. Accordingly, the chip performance, power consumption, and signal/power integrity have suffered from this increase.
To reduce the interconnect RC, copper and low-k materials were introduced. However, the new materials also brought with them great difficulties in manufacturing. Chip failures were reported due to low mechanical strength of the low-k materials, large thickness variation of the wires, or premature electromigration (EM) failure.
While the interconnect increasingly becomes a challenge, technology scaling continues. The smaller feature size allows larger and more complex system to be built on a single chip. The gate counts of a cell based ASIC product have increased from approximately 2 million in at 0.18 microns to well above 10 million in the 90 nm generation. Such large-scale, high performance, SoC designs make it difficult for ASIC vendors to meet the demands of turna round time, first-time right design, and high manufacturability.
The great challenges and the ever-higher demands require new solutions, which have been the driving force for the recent development of an interconnect-aware design methodology. This methodology has moved to high-level integration in multiple areas previously regarded as independent, such as design implementation, physical analysis, chip process, and packaging, because the problems we face today cannot be resolved in an isolated area.
The methodology requires a continuous convergence flow. In the traditional ASIC implementation flow, accurate interconnect delay can only be obtained at a late routing stage. But the freedom of modifying the design at this stage is limited. Most of the delay comes from the interconnect, so the tool flow needs accurate interconnect delay information as early as possible, and should allow continuous optimization in different stages to correctly reflect the real interconnect delay.
One may d raw the conclusion that nanometer IC design will have to involve many chip-level analyses with more and longer iterations. This could drastically increase the design turnaround time, which runs counter to the requirements of ASIC design. In order to solve this paradox, engineers at LSI Logic are developing a novel ASIC design flow with a clearly defined interconnect methodology.
An optimal interconnect architecture is the foundation of the methodology. The net delay can be divided into two regions. For shorter wires, the interconnect capacitance dominates the delay while for longer wires, the interconnect resistance plays a major role. Therefore, networks of short wires need thinner wires for lower capacitance, while the long wire nets benefit from thicker wires. This is why some published interconnect architectures use 4-5 different wire thicknesses for local nets and global nets, respectively. However, a thicker metal layer usually has to go with a wider pitch due to the maximum aspect ratio that the Cu/low-k process can support. Although more systems are being implemented on a chip, our design statistics indicate that with smaller feature size, the die size of our products is stable over generations, and the number of wires longer than 1 mm usually is low (< 5% of the total wires).
Nanometer IC designs are extremely susceptible to resistance and inductance- induced instantaneous voltage drop, because of the higher resistance, the higher signal frequency, and the lower noise margin. This issue is addressed in the steps of power planning, packaging, and placement along the flow. The appropriate package is determined by the total power consumption. To minimize the resistance of the power supply, the top thick metal layers are fully used to build the power mesh. The amount of decoupling capacitance needed for each portion of the chip is calculated to reduce the noise on the power lines which may result in a delay shift or wrong switching. p>
Interconnect heat dissipation of the signal and clock nets cannot be ignored any more because of the smaller interconnect size and poorer thermal conductivity of low-k materials. Part of the wires could reach a temperature much higher than the substrate temperature during operation, causing signal integrity degradation or reliability problem. In our design flow, the RMS current of each signal or clock net is analyzed to determine the wire width and the amount of via needed. In this way, the methodology guarantees that the current induced temperature increase in the signal and clock nets is within the spec under the worst operating condition.
As mentioned, a wire thickness model should be introduced in physical analysis to calculate the wire thickness based on the layout. The success of this approach depends on the consistency of the CMP process, parameter extraction, and model accuracy. This is a challenging task, especially in a foundry production environment.
As the first step, LS I has developed an avoidance-based methodology that takes the impact of the possible worst case variations on the signal nets into account in timing calculations. This methodology successfully addresses the issue of large interconnect parameter variation in the Cu/low-k process and minimizes the risk of timing failure.
For the nanometer Cu/low-k process, a design passing all levels of verification does not necessarily mean high yield. The Cu/low-k process makes the concept of "design for manufacturability" (DFM) extremely important. In our design flow, DFM is always one of the key considerations. For the Cu/low-k interconnect, wire density plays the important role in controlling the wire thickness. However, to set a density window is not an effective way to gain control. It unnecessarily limits the design capability. Our results show that to have a good pattern uniformity is a much better way to minimize the wire thickness variation. According to this finding, we have developed a unique dummy metal insertion methodology to achieve the best uniformity.
Nanometer ASIC design has been profoundly influenced by on-chip interconnect scaling. An effective design flow for the nanometer era has to have a design-aware and process-aware interconnect methodology. This methodology should be well integrated across multiple areas to address the issues effectively.