Designers of internetworking products face a number of challenges that dictate choices in chip design methodologies. The Internet is growing slightly faster than the formidable Moore's Law. Packet-processing requirements get more intense every year as the market demands more features. And customers increasingly want solutions that are programmable rather than hard-coded so that hardware can have a longer useful life.
Beyond these requirements, products in this space must meet such requirements as stability, reliability, high availability, scalability, density and low total cost of ownership. As a result, to stay competitive in this marketplace, design teams must do much more than just ride the wave of new silicon process technology. To maintain leadership, design teams are designing chips that now represent the bleeding edge in design complexity. Some chips of more than 250 million transistors, running at 400 MHz or more, have been fabricat ed. Still bigger and faster chips are under design.
The combination of speed and high transistor counts is putting a crunch on the interconnect that ties everything together on-chip. Interconnect introduces clock skew, crosstalk noise and increasingly consumes power-problems that will scale up with transistor count. Current CAD systems are able to handle those problems fairly well, but their performance on the next generation of chips may not be adequate. A central problem is predicting the longest wires in a design. These wires are the major culprits and will increasingly affect CAD tool flows. Studies looking forward at the effects of wire scaling indicate that average length wires will not pose a problem for CAD tools, but the occurrence of long wires will increasingly perturb circuit performance. Because die capacity is growing exponentially, long wires connecting on-chip modules will also increase exponentially. In order to prevent the corresponding increase in CAD tool exceptions, a better gras p of the entire flow will be needed.
ASIC design flows are simply not an option at that complexity and speed; a full-control, customer-owned-tooling (COT) design flow is required. To meet the product design challenges, Procket Networks formed close relationships with its electronic design automation and silicon suppliers, starting three years ago, to get the best tools and process technology. Where the commercial tools were not up to the challenge, Procket created its own.
The cost of developing an IC via a COT flow is potentially high compared with ASIC and FPGA projects because it takes more tools, engineers, and expertise to man the end-to-end COT flow. The development time to set up the flow is also longer. Once the design flow is established, however, chip designs can be processed rapidly, and sometimes more rapidly than with alternative approaches. In Procket's case, after the initial investment in the flow, the payback is coming in the form of turnaround times that are three to four ti mes faster than an ASIC flow.
Procket Networks' engineers chose COT because of a high value proposition and leverage of the flow for many tapeouts. We also saw a number of advantages to the COT model, the most fundamental of which is control. Design teams make their own decisions about tools, flows and methodology and COT design flows permit designer intervention at every stage in the process, without a huge time penalty. The COT flow is used to get and maintain full control over all options, and has been shown to deliver the highest performance with the smallest die size and power. COT designs also offer complete control over the design schedule. Success and failure rests in the hands of the design team.
Further, the COT design style permits innovation in design methodology. For example, parallelizing the front-end and back-end processes to create a pipelined implementation flow allows for continuous trials and refinements of the entire flow. In addition, typical estimates are that COT data paths have 30 percent to 50 percent faster performance and the die size is 25 percent to 50 percent smaller when using a COT flow vs. a traditional ASIC flow. These numbers are really the bottom line in the COT-vs.
-ASIC decision. Chip performance equals product value, and chip size equals product cost in the router market. Lower power consumption and higher system reliability as a result of higher levels of integration are additional benefits.
The philosophy used to craft a complex, high-performance IC design methodology should be to create an environment where designers can expend their efforts on the 10 percent of the design that is difficult, while the remaining 90 percent is serviced by a highly automated flow. The 10 percent part of the problem demands control.
To achieve speed in ICs, pipelined architectures are often employed. The same throughput advantages found in hardware pipelines can be gained in the hardware design process. Just like in a pipelined design, where the circ uit performance is limited by the slowest stage, in a pipelined design methodology the weakest link in the tool chain dictates outcome. Thus, there is a tremendous motivation to use only the best-in-class tools at every point in the flow.
Each type of tool has its own criteria for determining its best-in-class status. Synthesis, for example, must deliver the best quality of results (as measured by circuit performance and area). In this context, every tool needs to provide the highest capacity possible, and the best run-times. These shared factors have a direct impact on the productivity of the team and the success of the pipelined design methodology.
To make the design flow pipeline work, each IC must be partitioned into functional subunits that are of a size that is practical for the place and route tools.
This practical size for physical tools has remained at about 300k to 400k instances (or about 600k to 800k gates) for the last few years. This limit is largely driven by the practical capacity limits of the verification tools. Parasitic and transistor extraction tools have to deal with polygons, and in a 400k-instance module, there are usually around 40,000,000 polygons to process. Further, the 400k-block size limit yields manageable run-times for ECO scenarios that call for placement adjustment and rerouting.
For this project, the team created a set of automation scripts that divided the design flow pipeline into two major subsections, the front end (controlled by the easyFlow script) and the back end (controlled by the makeFlow script). A part of the rigor that was added to the project management was the use of weekly trial tapeouts that took the guesswork out of results that might be realized at the end of the process.
The multichip-product project has completed its IC design phase and working silicon has been incorporated into working systems. The innovative pipelined design flow used in conjunction with the best-in-class tools has now been shown to be capable of delivering some astonishing results. Contrary to popular belief, the choice of a COT flow achieved faster time to completion than an ASIC-based flow would have. In fact, Procket Networks' engineers achieved results that are much faster than the ASIC flow--two weeks from RTL freeze to tapeout.
Michael Raam is vice president of VLSI development at Procket Networks Inc. (Milpitas, Calif.). Bernd Braune is an adviser at Cadence Design Systems (San Jose, Calif.).