An integrated circuit at 0.25-micron design rules contains about 800 meters of wire interconnect, draining 50 percent of the power consumed by the circuit. When 0.01-micron chips emerge, they will typically have a total of 5 km of wire interconnect, all of it embedded in a piece of silicon only 2 cm on a side.
Those few statistics help to explain why simply getting signals from one on-chip device to another poses such difficult problems for the IC industry. The issue is being attacked on multiple levels: smarter circuit layout techniques, schemes for introducing a third dimension into interconnects and, at the physical level, copper conductors and low-k dielectrics. All of these techniques are helping to alleviate the physical burden of interconnect.
One thing is clear: Circuit designers need to understand the full scope of the problem if they want their designs to have a smooth ride through the test and manufacturing line. Intercon nect-generated faults have become a small nightmare for test engineers, who are struggling to find smarter ways to track them, mainly by inserting test structures into circuits at the design stage.
While more exotic materials or novel layout schemes such as diagonal wiring might head off some the the interconnect crunch, the main burden falls on state-of-the-art CAD system designers. A computer-aided design system must capture the salient features of interconnect to ensure that highly complex circuit networks are automatically generated in a way that makes implementation feasible. CAD system engineers are becoming highly educated in the problem, and in this week's In Focus, readers get a glimpse of the latest analysis and the strategies being used to deal with interconnect in system-on-chip devices.
Tim Saxe, vice president of engineering at Quicklogic Corp. (Sunnyvale, Calif.), and Brian Faith, the company's FPGA product manager, explain in their article how they are heading off interconnect problems in 0.18-micron designs. Their strategy centers on adding a sixth metal layer to their 0.25-micron process, which they employ to solve the long-interconnect-path problems that represent the worst case.
As circuits become denser, smaller transistors naturally speed up. But interconnect does the reverse, introducing path delays that cancel the speed increases of transistors. Currently, interconnect accounts for 75 percent of the path delay in circuits, the Quicklogic authors point out. Another scaling factor working against interconnect is the rise in aspect ratio with smaller size: The ratio of height to width increases, presenting large areas along the sidewalls of interconnect. The longer two wires run in parallel across a chip, the more capacitance and inductance effects degrade signals.
A second level of metal allowed Quicklogic's engineers to separate long wire runs physically, and a technique called "wire strapping" effectively allowed them to increase the cross-sectional area o f wires on the fifth metal layer. Strapping simply involves placing a second wire running along the sixth layer over a wire on the fifth, and connecting them at their ends to plugs running through the dielectric layer. The technique allowed Quicklogic to get the same performance for global wiring that would have been achieved by going to the more exotic process of copper and low-k dielectric.
Contributor Emre Tuncer, director of product development for the signal integrity flow at Magma Design Automation (Cupertino, Calif.), believes the looming interconnect crisis will only be met with integrated tool sets that address the complex issues posed. "Design flows using various point tools fail to predict final timing during early stages of the design," he maintains. "Ever-increasing complexity of SoC design, coupled with uncorrelated tool flows, makes it more difficult to achieve design closure on all fronts." Attaining that clo sure means heading off problems like crosstalk, electromigration, IR drop and antenna effects, all of which have a direct impact on the timing picture.
A variety of ingenious techniques are being tried to address the ballooning complexity of interconnect. One simple idea is to introduce diagonal paths into the layout. An industry group called the X Initiative is attempting to establish methods and standards for the approach, which is expected to reduce total wire length by 25 percent. It is fairly easy to introduce wiring that cuts corners at the design level, but what impact that will have on yield at the manufacturing line is still an unknown. Perhaps further into the implementation stage is copper interconnect, but that option is still not widely available to chip companies.
James Meindl at the Georgia Institute of Technology, who has become an expert in predicting the impending impact of physical parameters on future IC generations, has taken on the interconnect problem. His analysis pred icts 80 levels of metal by 2014 if no architectural changes are made in circuit design. That would be impossible to achieve.
One solution Meindl suggests is to get out of the passive-interconnect paradigm entirely. A simple way to make interconnect into an active device with more design parameters is to insert buffers or inverters at regular intervals. Those active devices will make the signal delay proportional to the wire length and thus help to minimize the reverse-scaling effects of passive interconnect.
The basic argument is that devices become more efficient as they shrink, while interconnect degrades in performance. What type of repeater and how many to include pose new design parameters that the engineer can use to optimize designs. Meindl predicts that the use of repeaters could reduce the projected number of metal levels to around 10, not 80, which would be an acceptable solution.
A true three-dimensional circuit capability would go a long way toward solving the interconnect problem, but researchers have been trying to make one for 20 years without much success. Theorists point out, however, that current semiconductor processes offer a high degree of multilevel capability, leading to the notion of 2.5 dimensions-that is, a large number of two-dimensional wiring planes, with more limited connections in the third dimension.
The introduction of novel wiring patterns-such as diagonal wiring or multilevel schemes for reducing interconnect complexity-offer some relief from the problem of interconnect, but they also complicate design tools or chip-manufacturing processes. Another approach is to find some physical way to reduce the penalty of interconnect with better conductors or insulators - an option that is becoming available as major semiconductor manufacturers introduce copper and low-dielectric-constant insulators into their processes. Copper has about half the resistance of aluminum, so an immediate benefit is gained in the RC delay factor.
While copper may solv e the designer's problems, it introduces several headaches on the process line. Standard etching processes do not work with copper: instead of removing material, aluminum based etching processes simply corrode the surface of the copper. Also, copper atoms are highly mobile in silicon and diffuse readily into neighboring devices, corrupting them. But despite those added complications, companies such as IBM and Motorola are successfully introducing copper interconnect and are achieving results in the form of higher-speed circuits.
Another possibility in this direction is the introduction of photonic waveguides for long interconnect lines. There is some hope here. With recent work on building photonic bandgap structures into silicon circuits, this might become a practical option for designers. Photonic structures can now be defined on-chip with the same lithographic processes used in CMOS manufacturing. Photonic interconnects do not carry the RC delay penalty that creates so many problems for wire inter connects.
While CAD tools can handle the increased interconnect of average-length wires, long interconnects are more difficult to predict. The unexpected delays or, worse, noise and crosstalk introduced by long wires can sink a design that is far into the process. In addition, the errors introduced by crosstalk are intermittent and difficult to track down at the test stage. Test engineers are working on special solutions for this problem that involve built-in self-test structures, which designers need to understand.