Downturn brings windfall
Downturn brings windfall
By Jauher Zaidi, President and CEO, Palmchip Corp., San Jose, Calif., EE Times
July 1, 2003 (3:52 p.m. EST)
Through the downturn, with thousands being laid off, the design workload is being left to fewer engineers. In order for them to meet their schedules and get chips into the market on time, they have turned to the system-on-chip platform and semiconductor intellectual-property companies to augment their design strategies. Acquiescing to the NIH (not invented here) syndrome is a luxury they can no longer afford.
There has been a definite uptick in recent months, with companies of all sizes looking for SoC solutions and IP cores to accelerate the design cycle and make up for lost engineering resources. Arguably, the increased activity can also be partly attributed to inventories' being depleted and to companies' de signing new products to refill the pipeline. In any event, there is reason for cautious optimism.
Another trend that is helping the SoC platform business is finding ways to accelerate time-to-tapeout. People used to say "time to revenue" was everything, but in the chip business you can't get to revenue if you can't get the chip to tapeout. This is where using SoC platforms as an integral part of the chip design methodology is really gaining traction. Geometries are getting smaller and smaller; the kinks are being worked out of the 130-nanometer node, and 90 nm is coming online. There is even a recent announcement of companies' building 65-nm fabs.
With this trend, it will become increasingly difficult to design a chip efficiently and get it to tapeout within a reasonable time frame. Design methodologies will have to change as the ugly rocks of timing closures, complex-chip routing and bus bottlenecks rise up out of the water. If these designs are to make it through the process, there can no longer be a hard division between the front end and the back end. The front-end engineer will have to design a chip that the back-end engineer can quickly and efficiently move through to tapeout.
To make that happen, new methodologies and tools will have to be made available to the front-end engineer that can be employed to accelerate the back-end process. Such functions might include on-chip networking to help with routing or dynamically adding pipeline stages to remedy timing closure issues.
For those who buy the products built with these chips, the main advantage of this trend in design is to drive the cost down by packing more functionality into a smaller device. This will, in turn, drive down the overall system cost and make technologies like GPS or wireless devices ubiquitous in the consumer market.
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