A typical SoC design requires IP procurement and development, complete system level verification and back-end design. Increasingly, SoC designers are emulating their design to perform functional validation to avoid expensive ASIC re-spins.
One approach to emulation is to opt for a commercial FPGA-based emulation platform for validating the SoC IP in a real world environment. Vendors such as Altrabit Networks provide emulation platforms to assist designers in two ways. One is SoC IP verification via FPGA based prototyping, and two, RTOS-based software development in parallel that keeps both the silicon design engineer and firmware engineer working in tandem to achieve the desired result.
The current leading edge FPGAs have compex IP such as RISC processors, high speed SERDES (Serial Deserializer ) and DSP blocks pre-fabricated in FPGA fabric. In addition they support multiple high-speed I/O interfaces to implement next generation bu s interfaces such as PCI Express, HyperTransport, RapidIO, networking and memory interfaces. These features make new breed of FPGAs ideal for implementing FPGA based SoC solutions or validating ASIC SoC functionality.
One thing to consider is that new complex FPGAs are expensive. Consequently, you have to mix and match, for example putting together high-performance IP in a complex FPGA, while low speed peripherals can be implemented in a cost effective production FPGA. This is a much more cost-effective approach than traditional high cost emulation systems, which prove to be too expensive and complex to use in an effective way.
Clear partitioning of a SoC design is a critical factor designers should keep in mind. The task CPU, memory, and high-speed logic demand a complex FPGA, whereas low cost peripherals can be implemented in a less expensive FPGA. If these two FPGAs are connected via a standards-based peripheral bus that could be used to implement the AMBA bus in an ARM CPU or OPB (On chi p Peripheral Bus) in the PowerPC architecture, the partition is clean. When the IP changes frequently, only that FPGA that contains the changes needs to be fitted.
For example as shown in the accompanying figure, Altrabit's silicon validation emulation platform has two FPGAs. The high-speed FPGA contains hardcore IP blocks such as a RISC uP, high speed SERDES and MAC/DSP, as well as, high bandwidth peripherals like DDR SDRAM controller, PCI-X, Gigabit Ethernet MAC to ZBT (Zero Bus Turnaround) SRAM are incorporated to achieve top performance. This FPGA also contains logic for a bridge that converts the processor bus to a peripheral bus such as AMBA on ARM or OPB on the PowerPC architecture.
Low speed peripherals such as the PCI bus, USB, UART, PCMCIA and others are implemented in the less expensive, less dense FPGA targeted for production volume. This partition saves lot of gates in a high speed FPGA, which can be used for a customer's logic. This FPGA-based emulation platform also provides several connectors for FPGA configuration, debug, and expansion I/O containing LVDS (Low Voltage Differential Signaling ) signal pairs for user defined IP. For example new emerging serial buses such as PCI express could be implemented and the interface is routed to the expansion connector to physically terminate the bus.
Since in a typical SoC design, a physical layer (PHY ) device is not integrated because mixed signal complexity and know-how, SoC IP validation can significantly benefit if a slew of PHY devices are available on the FPGA emulation platform. Sophistication and care have to be exercised to make sure the PHY devices work properly at much lower speeds compared to normal operational speeds.
This FPGA approach gives designers considerable latitude and the needed flexibility to use IP from third party vendors such as Synopsys, Mentor, Xilinx, Altera and others and allow them to mix their logic on the same silicon before they go into high volume ASICs or FPGAs.
This increas es probability of proven silicon during the first spin of the pre-production device, plus designers get the added benefit of having application software development in parallel with the silicon solution.
The SoC might have a PowerPC, MIPS, ARM, Tensilica, or ARC processor, several channels of high-speed I/O supporting up to 2.5 Gbps/port, DDR memory controllers, high-performance PCI/PCI-X bus, debug support like JTAG.
The prototyping evaluation platform is the heart of SoC IP verification, and it accelerates the development time by having firmware/application code early in the cycle and avoiding the time taken for multiple spins including fabrication lead times, backend design and post silicon validation, essentially cutting the total development cycle by one half.
The platform is low-budget for designers performing IP verification, as well as for embedded software designers doing software development. What can be most appealing to designers is the ease of use and cost effectiveness o f this hardware and software development tool. Further, a complete development platform like this helps the designer by reducing verification time in half compared to other methods and keeping design cost to a minimum.
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