Interface IP requires real-world validation

Any potential variation

As an example, SSTL 2 drivers deployed in a double-data-rate SDRAM memory interface will encounter a variety of loading conditions. Double-data-rate DQ (data) and DQS (strobe) lines can operate to data rates of 400 Mbits per second and higher, with loading conditions ranging from one board-mounted DRAM to several DRAMs residing on multiple dual-in-line memory modules. An address driver on the same interface can be expected to interface to as few as two and as many as 36 DRAMs at a data rate of 200 Mbits/s, or 100 Mbits/s if the net is heavily loaded and two-period clocking is implemented. A comprehensive analysis of the anticipated interfaces must include any potential variation in process, voltage and temperature. It must also account for the normal construction tolerances encountered in a typical signaling environment.

Timing and overshoot/undershoot analysis must be undertaken for the representative interface. The methodology used for the following discussion for the double-data-rate write interface applies to the read interface and the single-data-rate address and control signaling as well. DQ signaling of 400 Mbits/s yields a bit-unit interval of 2.5 nanoseconds. Assuming a centered DQS, the budget for setup or hold on the interface is 1.25 ns. Of this budget, typically 450 picoseconds is required for the receiving DRAM's setup-and-hold budget, leaving an 800-ps budget skew and jitter uncertainties contributed by the transmitter and by the interconnect.

In the transmitter itself, there are several line items that subtract from the timing budget. The penalty for simultaneously switching outputs requires extensive analysis in itself.

Accounting for skew

The interconnect budget must account for skew between the DQS and DQ on the board and within the package as well as jitter resulting from pseudorandom signaling of the interface. Allowing 100 ps for skew contributions leaves a budget for eye pattern jitter of 280 ps for setup and 480 ps for hold. Much of the information required for the timing budget is available from data sheets or is determined during the initial circuit design. The bulk of the simulation effort goes into determining the setup-and-hold jitter introduced by the interconnect.

Once an interface has been selected for simulation, a pseudorandom signal is launched onto parallel DQ paths. The spice deck makes a series of setup-and- hold measurements to the DQS strobe to determine the minimum setup-and-hold times. A time of 1.25 ns minus the smallest setup-and-hold values measured yields an uncertainty value that must be subtracted from the appropriate setup or hold budget. Transmitter contributions, DRAM setup-and-hold requirements, interconnect skew and measured setup-and-hold jitter must total less than 1.25 ns to support 400-Mbit/s write timing under worst-case conditions.

Best and worst

To determine the suitability of an I/O cell to a particular interface, the following parameters are varied during the simulation. Silicon process is varied from SS to TT to FF (logic states). Cases with slow p channels and fast n channels and vice versa are also examined. Core voltage and I/O voltage are varied plus/minus 10 percent from nominal. Temperature varies from 0 degrees C to 125 degrees C.

Best-case and worst-case package models are used in the simulation. The simulation deck will sweep the board impedance environment through the range of characteristic impedance and propagation delay tolerances, usually plus/minus 10 percent or greater. If the interface employs parallel termination to Vtt, this resistor will be cycled through nominal Zo plus/minus 10 percent. Three parallel DQ lines and one DQS comprise the interface. The simulations capture the crosstalk-induced jitter for both even and odd switching cases when the center DQ signal is of the same polarity and opposite polarity, respectively.

This series of simulations is repeated for case s that represent the heaviest and lightest loading at the highest frequency expected in application. After the completion of the initial analysis, the interfaces fall into three categories. The first are those that the I/O cell cannot support, usually because of heavy loading or extremely high frequency.

The second category contains those interfaces that can be implemented with the minimum of additional engineering effort. These are usually fairly lightly loaded. The third category covers those cases that will work, but will require careful signal integrity analysis to assure proper functionality. To ensure the functionality of these interfaces, it is critical that designers have access to this type of analysis either from in-house resources or from their IP provider. Ideally, this kind of testing includes signaling environments with scripts for measurement and data parsing. These are extremely useful for evaluating new interface iterations that emerge later in the customer's product life cycle.

Interface IP cannot be designed in a vacuum. Sound design requires full cognizance of the signaling environment and the ability to quantify the effectiveness of IP in that environment. With extensive simulation suites and application notes, efficient deployment of IP can be assured.

John Ellis is the vice president responsible for signal integrity at TriCN Inc. (San Francisco).

See related chart When multiple signals switch simultaneously, AC ripple causes the power rail to collapse resulting in increased delay through the DQ (data) driver. The magnitude of signal pushout correlates to the amount of ripple on both the core and I/O power rails as depicted in the table. For a DDR (double data rate) interface, this additional delay corresponding to the ripple is charged against the set-up budget when measured to a DQS (strobe) 90 degrees out of phase. Knowing how much push-out will be generated lets the user determine how much ripple can be tolerated and how much decoupling is needed.

See related chart

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