Speed, power crunch looms for wireless

Designers of user equipment must also offer improvements in user interface (such as color screens), longer battery life, lighter weight and competitively small form factors. There are many engineering challenges imposed by new air interfaces as well as the expectations of these nascent markets.

Legacy support

Despite the proliferation of new air-interface standards, the market continues t o demand support for the legacy standards (analog, GSM, IS-95A, B) and their enhancements (Enhanced Data Rates for GSM Evolution, General Packet Radio Service) in addition to providing new functionality offered by 3G and beyond. Besides traditional cellular telephony (voice and data), additional opportunity lies in untethered networking markets such as Wi-Fi (and all of the 802.11 variations), Bluetooth, 802.15 and ultrawideband, among others.

The expectation has been that all the enhanced capabilities would come at a cost below that of today's products.

Digital signal processing is the technology that will drive this migration and enable the new generation of products. DSP for the wireless market describes a technology, not a device category. It is digital signal processing as a solution technology, not just the DSP devices.

An often-quoted aphorism holds that "If the only tool you have is a hammer, you treat everything like a nail." Unfortunately, this is an accurate description of the rationale for solutions proposed by some vendors attempting to address baseband processing.

Recognizing the dichotomy in the two diverse categories of baseband processing (and including two more cliches in our message), most designers prefer to use the right tool for the job rather than forcing a one-size-fits-all approach.

If we focus on direct-sequence spread-spectrum air interfaces such as wideband code-division multiple access (W-CDMA) and cdma2000 (the two most popular 3G air-interface standards), it is easy to divide baseband processing into two general categories of tasks. One subset of these processing tasks is repetitive, compute- intensive, relatively simple jobs. Here, the chip-rate correlation tasks are the most prominent elements. The other subset covers more irregular functions that call for complex decision-tree/branching types of operations as well as for significantly lower processing rates.

When designing modems for these markets, the irregular, complex functions have been and will probably continue to be served by DSPs. These solutions bring all the flexibility of programmable devices and the associated benefits of software-based implementations. This portion of the digital signal-processing task will profit from the continuing progress in process technology (small geometries, smaller die sizes and lower cost, lower power, faster clock speeds and so on).

In the repetitive, compute-intensive class, traditional DSPs have proved to be a poor fit. Hardware-based solutions (ASICs, FPGAs, coprocessors) have been used effectively here because of their inherently lower cost and lower power consumption. Unfortunately, there are demands from the market that complicate the application and reduce the utility of these devices in 3G wireless systems. ASICs, FPGAs and coprocessors are selecting themselves out of future wireless systems.

First, it is almost an oxymoron to refer to 3G standards; the air-interface options are numerous and they will continue to evolve for years. It is a challenge to deliver a system that can confidently accommodate the evolution of even one of these standards with such inflexible approaches as provided by the historical hardware-based solutions. Should an OEM choose to deliver products for multiple air interfaces, it must decide whether to serve those markets by building multiple market-specific modems or by building a single modem with air-interface-specific blocks.

One problem with building market-specific modems is that the approach does not permit the OEM to take advantage of economies of scale and it multiplies the development costs almost linearly by the number of different modem designs delivered.

Designing a single modem with the potential to serve multiple air interfaces has the disadvantage of increasing the end unit cost by adding to the design complexity (higher development cost) and including circuitry that is not utilized by each interface supported (higher die size, higher silicon cost).

Not only th at, but the development of large ASICs (multi-megagate devices) has seen a rapid rise in engineering costs as the design and verification tasks increase exponentially in magnitude. The costs of manufacturing ASICs in leading-edge process geometries are startling (mask set costs alone can exceed $1 million) and the projected growth of these markets before the next spin is required by standards flux and unpredictable market needs does not permit amortization of these NRE expenses over large volumes.

To address these deficiencies in the traditional approaches and permit a compelling business case for the OEM, reconfigurable solutions for these portions of the modem will be required. Motorola's Smart Baseband is a multitechnology solution designed to address the needs of baseband processing in 3G basestations. At the center of the Smart Baseband are new members of the StarCore-based 81xx family of high-performance DSPs. The recently announced MSC8122 and MSC8126 offer high computational rates, a simple p rogrammer's model and the appropriate balance of peripherals required to provide the core intelligence of the solution.

Moving closer to the antenna, signal-processing demands are staggering. One can encounter sample rates of tens of megasamples/second from each antenna; receiver task loads are measured in billions of operations per second. It is clear that commercially viable solutions require a different technology than the traditional DSP. This is where the vendor's toolbox has to have more than just the hammer described in that famous adage.

Motorola's Reconfigurable Compute Fabric technology specifically addresses compute-intensive applications such as these. The MRC6011, announced in June, embodies this technology. Initial samples of this device deliver 48 billion complex correlations per second (eight-bit I & Q). While this is a necessary element of the chip-rate processing task, it is important to note that the device can also deliver up to 24 billion DSP-style operations/s for the re maining baseband processing tasks that follow the despread correlation. Equally essential, the MRC6011 addresses the spreading, modulation and coding tasks of downlink (base-to-mobile) processing.

Completing the system-level view of the Smart Baseband suite, Motorola offers a range of options to fill the requirements of the host processors and network interface (PowerPC host processors, PowerQuicc communication processors, C-Port network processors, serdes transceivers, clock drivers, encryption processors, etc.).

Silicon is the tool; software provides the solution. Tomorrow's vendors are being required to provide an ever larger portion of the basic system software. Customers faced with tight product schedules, lower team head count and aggressive cost targets simply can no longer afford to invest in the development of the base functions and must focus their limited resources in those areas where product differentiation is possible.

The 3G market presents the solutions vendors with a large challenge. These air interfaces are far more complex than the existing air interfaces, yet the market demands a cost per channel of less than one-tenth the cost per equivalent voice channel. Programmable/reconfigurable digital signal processing is the technology solution to meet these challenges.

Roman Robles is manager of the digital technologies operation at Motorola Inc.'s Semiconductor Products Sector, working in the Networking and Computing Systems Group, RF and DSP Infrastructure Division (Arlington Heights, Ill.).

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