Synopsys DesignWare Verification IP and Vera Accelerate Complex SoC Validation

Developing soft IP for cryptographic engines prompted Discretix’s verification engineers to consider more efficient and robust alternatives for their verification methodology. Tomer Labin, hardware manager at Discretix Technologies Ltd, explains how adopting a combination of Synopsys’ Verification IP (VIP) and Vera improves project development time and enhances confidence in verification sign-off quality.

Wireless connectivity—mobile, WLAN, or short range technologies such as Bluetooth and RFID—presents many challenging design issues. As data rates for wireless terminals steadily improve, the wealth of applications open to users of these platforms is rapidly expanding. Users are demanding the same access to data that they enjoy from their desktop environments. Activities such as banking, shopping, and remote access to corporate networks through Virtual Private Networks (VPN), are all possible from wireless terminals.

Security over the wireless network is a key issue for users and network operators. The applications mentioned above require a robust security solution. Traditionally, security solutions for such applications have been computationally demanding. At the same time, portable devices share two important characteristics. First, the resources available are scarce—limited computing, memory, and power. Second, cost is invariably a key issue.

In facing these constraints, some solutions have relied on software to implement security. Although this satisfies the cost constraint, the solutions are often sub-optimal because they consume resources that are desperately needed to implement peak computing demands, such as baseband processing.

Developing Soft IP for Cryptographic Engines
Recognizing the compelling need for security across wireless connection—the particular resource constraints that portable devices present—our team developed efficient silicon intellectual property (SIP) security solutions specifically for mobile handsets, smart cards, wireless LAN, and Bluetooth products.

CryptoCell is a complete security toolbox, providing a robust, high performance, security solution that meets the specific needs of the mobile phone market. It covers all aspects of security, starting from common security algorithms, through security protocols and application interfaces, all the way to protecting sensitive data and software code. By providing a full- cryptographic engine in hardware, manufacturers of wireless infrastructure and terminals can execute secure applications on mobile terminals with high performance, ensure minimum loading on system resources and offer maximum security.

We provide the cryptographic engine as a soft-IP core. This ensures maximum flexibility in integration and implementation for our customers. Because our engines will be integrated into a customer’s SoC designs, it is important to select a bus protocol that is compatible with our customer’s requirements. ARM’s open standard on-chip bus AMBA—has significant market share in wireless products, and from a technical perspective it meets our design needs.

Key Verification Challenges
With our design built on an AMBA bus structure, one of the most important things we needed to get right at the outset was the accuracy of our AHB master design. To achieve this we required an accurate AMBA AHB model. This enabled us to prove that the design was error free, and also ensured that it was fully AMBA AHB compliant under all conditions—not just the particular configuration we were using.

We chose to use the Synopsys DesignWare AMBA Verification IP. We required a verification testbench environment that could be set up quickly and easily, and one that would deliver accurate and comprehensive testing based on the AMBA standard. The DesignWare AMBA VIP includes the features we require. One of the important benefits is the availability of constrained random testing (CRT) from the VIP blocks within the existing HDL verification environment.

Setting up the testbench was straightforward. Our design was configured as a master on the AHB, with the AMBA VIP providing AHB slave emulation (Figure 1). While this interface is used only for data transactions, the other interface (APB slave) is used for configuration, enabled by using the AHB to APB Bridge from the DesignWare Library. Another master (beside the CPU and SDMA) was added to the system, enabling us to emulate a multi-master environment. For this we used the AMBA VIP AHB master.

Figure 1. Generic System with AMBA Bus Modules

The AHB master initiates transfers and bursts onto the AHB. The AHB slave responds to transactions while the AHB monitor observes the resulting activity. The monitor performs protocol checking, transaction logging, and functional coverage monitoring.

Initially, our verification environment was developed using Verilog. The DesignWare VIP worked with this environment and immediately gave us an accurate logic model that improved our ability and efficiency in verifying the AMBA bus infrastructure.

Because the DesignWare VIP makes use of the OpenVera™ language, migration of our verification environment from Verilog to Vera®, the Synopsys testbench automation tool, was a natural step to take. We benefited from moving to Vera with a further increase in productivity.

For this project, we completed the migration from a Verilog-based verification environment to an environment based on Synopsys Vera and DesignWare VIP. The whole exercise took about two weeks to complete. The few problems that we did encounter were easily overcome with the excellent support that Synopsys provided.

With this combination of tools and VIP, it is possible to exercise the full range of the bus protocol with a few commands. Vera makes developing tests within the entire environment (especially constrained random test) much easier, and has given us another boost in verification productivity.

Future Verification Foundation
With the ability to take complex AMBA parts such as the AHB master and AHB slave ‘off the shelf’ from the DesignWare library, the time needed to build complex verification environments is very short. Currently, we are undertaking our second project with the new Synopsys Vera and VIP based environment. We feel that our verification is more efficient and higher quality than before, and we expect to continue to use these powerful tools as the foundation for all verification at Discretix.

Discretix Design Environment includes the following: Synthesis: Synopsys DC Expert™ Power Optimization: Synopsys Power Compiler™ Static Timing Analysis: PrimeTime® Design For Test: TetraMAX® ATPG Testbench Automation: Vera® MTI ModelSim Simulator DesignWare® AMBA™ Verification IP (VIP) ARM 926 Design Simulation Model (DSM)

DesignWare VIP Synopsys DesignWare AMBA Verification IP (VIP) provides efficient verification of AMBA-based SoC designs. Features include the following: AMBA 2.0 compliant Supports the following: All AMBA 2.0 data and address widths All protocol transfer and response types AMBA, AMBA-Lite, and multi-layer AHB Constrained randomization of protocol attributes Logs transactions and reports on protocol coverage Offers user-configurable message formatting Provides full support for VERA, Verilog, VHDL, and C verification environments

Tomer Labin’s career has included positions with Intel Israel and Galileo Technology (now Marvell). He has held the position of hardware design manager with Discretix for the past two years.

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