The winners in the system-on-chip revolution are winning because they have adopted system-level design tools and methodologies. Leading designers are using these approaches because traditional methodologies cannot deliver the orders-of-magnitude increases in design productivity required to meet modern SoC design challenges.
For example, STMicroelectronics attributes its SoC business success to its early adoption of system-level design. Similarly, Sony says its system-level design methodology enabled it to deliver a leading-edge digital camcorder seven months ahead of a name brand rival's product.
What are the design challenges driving this methodology change? SoC technology now enables the integration of diverse functions-such as wireless communications, MP3, digital imaging and video playback-into one multiprocessor, complex system-on-chip, with rich embedded software content. Designing such a chip requires the iterative developmen t of the complex algorithms and architectures that determine the cost and the performance of the end product, such as quality-of-service, interoperability and power consumption.
According to International Business Strategies, the SoC architectural design effort will overtake the physical design effort at 90 nm. Further, the embedded software development effort will overtake the hardware design effort at 130 nm. Thus, designers require a dramatic reduction in architecture development time, much earlier software development, and much earlier and faster SoC verification (particularly hardware/software co-verification). Without major productivity increases, next-generation SoC time-to-market and design costs will skyrocket.
How did SoC leaders such as STMicroelectronics and Sony devise winning methodologies to solve the problems? They simply repeated the industry's history of progressing to a higher level of abstraction at each productivity bottleneck-a progression that occurs every decade in res ponse to Moore's Law.
The leaders deploy tools and methodologies, utilizing the C++ and SystemC languages that simulate a complex SoC and its embedded software up to 500,000 times faster than the traditional RTL approach. Thus, they can rapidly explore and evaluate multiple, often fundamentally different architectural models to determine the one that best achieves the market-driven design objectives. The duration of the effort is cut from months to weeks.
The leaders then use this optimum system-level model-or transaction-level virtual prototype-to develop application software in advance of RTL implementation, and system software in parallel with it, winning several critical months. And they verify the software at more than 100,000 bus transactions per second-significantly faster than at the RTL/C level.
Finally, they use the models as the foundation for a reusable platform-based design infrastructure that spawns multiple fast-turn derivative designs. Such a system-level infrastructur e provides an environment in which the latest-generation processors and other intellectual property may be readily evaluated and the design rapidly modified to produce a "new" design to meet the changing market need.
In short, the leaders ensure that the big picture is correct at a higher level of abstraction before embarking on RTL implementation, thereby avoiding time-consuming RTL design iterations. And software development begins months before RTL design availability.
The resulting orders-of-magnitude productivity increase enables the leaders to deliver designs and derivatives with the rapidity and frequency necessary to win the SoC revolution.
Tim Herbert is vice president of CoWare Inc. (San Jose, Calif.).