SANTA CRUZ, Calif. Users of Synopsys' memory intellectual property are generally pleased with the memory controller and memory model that comes free with the DesignWare library, but some want RTL source code, according to postings in this week's (Oct. 2) E-Mail Synopsys User's Group mailing.
Without it, several users noted, the memory controller must be compiled to gates to work with non-Synopsys simulators.
The ESNUG 418 bulletin provides a follow-up to ESNUG 415, in which 24 users of Denali Software's memory IP expressed mostly positive views of that company's product. Both bulletins are based on a user survey conducted by ESNUG moderator John Cooley after a Synopsys representative questioned why users would buy Denali IP when they already have memory IP in their DesignW are libraries.
A dozen DesignWare users shared their experiences in the latest ESNUG bulletin. They are working with a variety of memory types, including SRAM, SDRAM, DDR-SDRAM, SSRAM and flash. Supported memory devices ranged up to 256 Mbytes.
Most said the DesignWare memory controller met their performance requirements, although one engineer said he had to add some glue logic to make it work with SSRAM. Another said it worked for SRAM and flash controllers but fell short of the DDR (double data rate) target.
Asked to compare the DesignWare and Denali memory models, most respondents said they hadn't used Denali. One said the Denali memory models "seem to be more accurate." Another said the only advantage of Denali memory models is they they run on PCs using Windows. A third said Denali models link with Synopsys' own Vera verification environment more easily.
Several complaints emerged when users were asked if the DesignWare memory controller supported existing synthesis and simulation flows. "I'm using Cadence NC-Sim," wrote one engineer. "Because the memory controller RTL is encrypted and then usable only by Synopsys tools, I have to do a simulation using a GTECH [general technology library] mapping."
"We ran into problems while using Cadence NC-Verilog and had to use a gate-level netlist to proceed with RTL simulation," wrote another. A third engineer, who did not identify the simulator he used, also spoke of having to compile to a gate-level GTECH netlist.
Phil Dworsky, director of marketing for the Synopsys DesignWare library, said Synopsys offers both source and encrypted versions for its AMBA bus and peripheral solution, including the memory controller. But the encrypted RTL models are provided with the library for free, while the RTL source must be separately licensed.
Kevin Silver, Denali's vice president of marketing, said his company offers RTL source, testbenches for simulation and scripts for synthesis and static timing analysis along with its memory controllers.
In the ESNUG survey, respondents did not report problems with the memory controller in physical layout or test. Most said the memory controller matched size estimates. Most also said Synopsys offered good customer support, although there were several complaints about bugs.
Complaints about the lack of RTL source resurfaced when users were asked if they'd use DesignWare memory solutions again. "I would definitely use the DesignWare solution, except the source should be made available as we will be restricted to run only with [Synopsys] VCS and we cannot go to any other simulators," said one engineer.
"I would think twice and, if possible, avoid the DesignWare memory controller," wrote another. "It is difficult to work with any IP that you do not have access to the source code."
Still, the convenience of not having to buy third-party memory IP is a significant draw. "We already owned the Synopsys DesignWare license, and it did not make sense to continue using the Denali solution," wrote one. "It [the memory model] is included with the license we already purchase from Synopsys," wrote another. "It seems to do the job well and is easy to use."