SoC: Stuck in the mud or Charging ahead?
By Ron Wilson, EE Times
October 14, 2003 (8:42 p.m. EST)
As an application for future systems-on-chip, consider the 3G-cellphone wristwatch. Functionally, it would combine a cellular phone with an integral antenna, microphone and speaker. A small color display with a touch-pad interface and a miniaturized color camera capable of generating low-resolution video or moderate-resolution still images would be likely user interfaces. And, e-mail with multimedia attachments, instant video messaging, audio and movie entertainment playback and interactive games would be other built-in applications.
Our hypothetical device would clearly push the boundaries of the concept of system-on-chip.
Such a system would integrate digital circuits with analog and passives.
There will be plenty of digital circuits to integrate. A 3G phone requires much greater baseband processing than today's 2.xG phones, so there wil l be more dedicated DSP hardware. The graphics processing for games and the compression and image processing for photos or video will require specialized hardware as well. This processing, plus the need to get anything like smooth video over a 3G packet network, will require substantial amounts of local memory.
But very few researchers see the raw amount of digital circuitry as an issue. Despite the growing unease about the far future, Moore's Law is likely to carry us well into the densities that would make this sort of SoC possible. The issues arise when you start looking into the kinds of circuits involved.
And the first of those issues is at the heart of any digital phone design: non-volatile memory. Of the plausible technologies, only flash is currently viable for embedding large numbers of bits-and for 3G, we are talking about a lot of software. But embedded flash is a process integrator's bad dream: it requires significant process changes and a floating gate with a very thin, perfect d ielectric. For this reason, embedded flash processes lag at least a full generation behind their digital-only flagships. Worse, it now looks like the flash cell simply won't scale much below 90 nm.The alternatives?
Most SoC players are working frantically on either ferroelectric RAM (FRAM) or magnetoresistive RAM (MRAM.) Both of these structures may scale. But both introduce foreign, poorly understood materials into the process, and neither has been proven in an embedded production application, grand claims aside.
The most likely solution to the program storage problem on our wrist is another existing technology: the stacked package. This will permit an arbitrarily large amount of flash (or whatever) to be packaged with the SoC, without significantly increasing the footprint and with only sheet-of-paper impact on thickness. A good solution, but it's not, really, a solution on chip.
Analog circuits-remember the speaker and microphone-create another decision point. Data have repe atedly shown that most of the re-spins on SoCs are due to analog circuits, and managers are increasingly reluctant to include them if there is any alternative. Once again, the stacked package comes to mind.
But here Brian Evan, the general manager of the Broadband group at Texas Instruments, begs to differ. "At TI, we see more spins for digital than for analog problems," Evan said. "Successful analog integration isn't impossible; it's a matter of doing your homework. You need to have steps in the process from the beginning to ensure good linear components, and you need to characterize the devices for analog use early on, not as an afterthought."
"Things like increased isolation, good poly resistors, dense capacitors and good high-voltage devices need to be there," added advanced wireless architectures manager Bill Krenik. "And it's not just steps; it's controls. You need control of implants to manage body effects and to get stable drain conductance, for instance." With these additions to the process-none of which is insurmountable, but none of which is trivial-and with equally attentive circuit design, the TI managers argue, integrated analog is a reality, and will stay that way.
But our wrist won't just need analog; it will need analog at radio frequencies. And RF is another kettle of fish. Relatively low frequencies at moderate power with undemanding distortion and noise requirements are possible now: TI is planning to ship a Bluetooth chip with integrated RF later this year, and an integrated GSM RF/baseband in 2004. However, that is a long way from putting the RF for even current CDMA, let alone 802.11g or 3G, on an SoC. Most people see separate RF chips or stacked packaging as an answer.
Power is another issue. Obviously our speaker or headphone driver will require power transistors. But audio amplifiers are getting integrated into digital chips today-it just takes very careful proc ess modeling, fanatic attention to noise paths and specially designed transistors. And, it's not a piece of cake either.
A less obvious issue is the power supply. Some designers studying power and clock distribution problems are concluding that the huge amounts of metal necessary to manage voltage droop and clock skew are becoming unsustainable, particularly with the emerging problems in advanced interconnect stacks. So they are turning to point-of-use regulators and clock generators embedded in high-consumption circuit blocks. Analog Devices, for example, uses local linear regulators to supply current to the VCOs on some of its RF chips.
TI is using multiple on-chip switching regulators on some SoCs. Not only does it ensure adequate regulation, but on a multi-voltage chip, it vastly simplifies board design. But here again the stacked package is alluring. Some designers have discussed creating a chip that is just an array of voltage regulators, and bonding it face-to-face with the signal chip so that the regulators are right above the blocks they supply. Passive resistance
Looking at the innards of your current cell phone handset, you might be hard-pressed to find the SoC in the forest of discrete transistors and passive components. "Attacking all those passives with integration is very attractive," observed ADI director of business development Doug Grant. It is possible to fabricate resistors, capacitors and inductors on-chip, sometimes with the aid of a second poly layer. The problem is that the devices are never quite what you could get as discretes-particularly in the quality factor of capacitors and inductors. And they take up a relatively huge amount of real estate. You have to ask if it's worth it to have a mediocre on-chip inductor as big as a 32-bit CPU.
Analog Devices product line director Dave Robertson said the starting point was to throw out your existing circuit design and to start over on a design that minimized the number of passives and the sensitivity to their quality. Both analog circuit changes and digital compensation could be used to get adequate performance out of poorer on-chip devices, Grant added. But, again, is it really worth it? Once again the idea of adding one more substrate to the stacked package beckons.
| A deep silicon etch created this MEMS optical switch. |
At the Inter-University Microelectronics Center (IMEC; Leuven, Belgium), researchers are taking that idea one better. A team there is fabricating high-quality thin-film inductors directly on top of the passivation layer on conventional ICs. IMEC is reporting inductors with Qs of nearly 40 at around 5 GHz using this approach. The process takes up no silicon real estate and appears not to compromise yields. It is even possible to create three-dimensional structures, such as self-assembling helical inductors. A case of the mems
Bringing up three-dimensional devices raises the whole issue of MEMS. Our device will need an antenna switch, which could be implemented in GaAs or as a mechanical switch. It will need a microphone and speaker, which could be implemented as MEMS, and it might even be able to use a structure something like the TI light valve technology for its display. Can MEMS be integrated on our system-on-chip?
Here the technol-ogy news is good. Production devices, such as accelerometers for air-bag use and RF switches with control logic, routinely integrate a MEMS structure with active circuitry. And there are approaches that permit MEMS to be fabricated either in a cavity underneath an SoC's active layer or on top of its passivation. These techniques could be used for simple passive components, for switches and transducers, or for whole machines.
But once again reality intrudes. Silicon isn't anyone' s choice for the best material from which to fabricate MEMS, though it is used. Worse, lithography for MEMS requires depth of field not available on deep submicron steppers, and some of the process steps can require temperatures that are hostile to ICs. And there is the known-good-die problem in spades.
Finally, MEMS packaging and test requirements can be radically different from those for conventional SoCs. Consider the humble accelerometer. "Imagine the look on the face of a production test engineer when you bring a thing like a giant paint shaker out and set it next to his ATE system," offered ADI's Robertson. Once again it may be more economical to rely on stacked packaging, or even side-by-side packaging, to integrate MEMS with our SoC.
"It comes down to economics," declared Andrea Cuomo, corporate vice president for advanced systems technology at ST Microelectronics (Geneva, Switzerland). "There are few unsolvable technical problems in integrating just about anything onto an SoC. But it usually comes down to two questions: is this a valuable use of die area? Does this integration make business sense for us and for the customer?"
For example, what does adding complexity to the process do to the cost? In addition, given the process, what does adding area to the die to include the device do to the cost? Will the integrated device be testable? Flexibility is another point Cuomo drove home. What if you have two customers who want slightly different RF stages? Your integration strategy could backfire. "We will do single-chip systems if the application is so stringent as to require it," Cuomo stated. But often, many experts agree, a stacked package that allows different kinds of devices to reside on their own substrates looks like a much better alternative to the true system-on-a-chip.
On the way to true system-on-single-chip, the semiconductor industry may first explore the system-in-a-stack.