Rapidly Implementing Synthesizable ARM IP (By Alan Gibbons, Synopsys and John Biggs, ARM)

Through the results of a unique technical collaboration between ARM and Synopsys, the process used by ARM licensees to port synthesizable ARM® microprocessor cores to their chosen technologies, has been significantly streamlined. The ARM-Synopsys Reference Methodology represents the set of best practices for implementing synthesizable ARM IP with Synopsys tools and provides a proven, low- risk solution to providing application specific ARM intellectual property (IP).

ARM, the leading provider of 32-bit embedded RISC microprocessors with almost 75 percent of the market, offers a wide range of synthesizable processors based on a common architecture that delivers high performance with low-power consumption and system cost.

ARM synthesizable processors are delivered to licensees in a soft form at the RT level and can be targeted at a variety of technologies to yield specific implementations. The hardened ARM processor can then be deployed as a reusable library level component in an ARM core-based system chip.

Application Specific Hard IP
IP is typically provided in either hard or soft form. Hard IP is technology dependant and has predictable characteristics. However, because the IP has been pre-implemented its application is limited and this predictability comes with a cost. Soft IP is highly flexible but presents the IC designer with a certain degree of risk because its characteristics are not defined. Application Specific hard IP seems to offer the best of both worlds. Here, the IP is deployed in hard form, but the implementation of the hard IP is specifically targeted at the system-chip application using a proven methodology. This solution provides the system-chip designer with the flexibility of soft IP together with the predictability of hard IP.

The process of implementing application-specific hard IP is conceptually very similar to a compiled memory. The designer configures and verifies the RTL description of the IP, defines the specific characteristics including target technology, device topology, memory, test strategy and so forth, and compiles the design to yield a GDSII representation together with a set of models, or abstractions, that are referenced by the system-on-chip (SoC).

Proven Methodology Is Key
For application-specific hard IP to be commercially viable, the soft IP must be implemented rapidly without sacrificing performance, power or area. The resulting implementation—modeled completely for the core—can be deployed as a reusable library level component. A proven methodology for the implementation of soft IP enables the rapid deployment of a complex processor into an ARM core-based system chip.

The effort required to harden soft IP is a function of the quality of the target technology, the design goals, and the methodology employed. Both the target technology and the design goals depend on the target SoC, and what may be achievable with one technology may not be achievable with another. However, the methodology employed to implement this IP can be common across different licensees. Investigations have shown that a single proven methodology yields good results for the majority of CMOS technologies.

Figure 1. ARM-Synopsys reference Methodology

ARM and Synopsys have been working closely to develop a proven methodology for the implementation of synthesizable ARM IP using Synopsys tools. This methodology, called the ARM-Synopsys Reference Methodology, is a fully integrated implementation platform based around Synopsys’ Galaxy SI Design Platform, an open, integrated design-implementation platform built on best-in-class EDA tools.

The methodology provides complete support for the hardening and modeling of synthesizable ARM processors using a physically aware based flow with integrated SI capability for design closure when targeting leading edge technologies at 90nm and below.

The flow is based around Physical Compiler for synthesis and Astro for clock distribution and routing. Specific capabilities that are tightly integrated within Physical Compiler® include the following:

• RTL clock gating with Power Compiler™
• Design for test support with DFT Compiler™
• Datapath synthesis with DesignWare® Foundation
• Compile strategy support for DC Ultra™

High-level integration within Physical Compiler ensures that an optimal implementation can be created quickly thereby providing a rapid synthesis flow that creates an optimized placed-gates netlist with excellent correlation to post-layout timing. The compile strategies employed within the Reference Methodology are a result of numerous investigations on a number of competitive CMOS technologies at 180, 130, and 90nm. Although results will vary as the processor is ported to different technologies, the fundamental principles employed in the methodology hold true from one technology to the next.

Figure 2. Synopsys Integrated Tool Flow

The layout phase of the reference methodology provides a similar level of integrated support from within Astro. Support for clock-tree synthesis, global and detailed routing, parasitic extraction as well as verification through the use of DRC and LVS are all integrated seamlessly within the Astro environment.

Static Verification Enables Time-To-Market
In addition to a physically aware synthesis approach, static verification methods are employed to speed verification at various stages in the implementation flow. Dynamic simulation with VCS is used to validate the RTL image of the processor after configuration. All subsequent verification of the design’s functionality is performed statically with Formality and the timing is verified statically with PrimeTime-SI.

Complete Modeling Support
Rapid implementation of the processor in a target technology is only half of the job. To deploy the hardened processor in a system-chip environment, the processor must be represented as a library-level component. This requires accurate, sign-off quality models of the processor to be created from the final implementation. The processor models represent the key characteristics of the processor while hiding unnecessary and proprietary implementation information. To avoid prescribing the SoC design flow, these models must be provided in industry standard formats usable by commercially available EDA tools.

Figure 3. Complete Modeling Support

Generating these models is an integral part of the hardening of an ARM processor. Greater efficiency and correlation are achieved when these models are created automatically as a part of the implementation process. This results in a single-pass flow that yields an optimal implementation with a GDSII representation plus the associated functional, timing, test, and physical models.

The functional model is an implementation specific sign-off simulation model based on the final gate-level netlist. The functional model is created from the layout netlist using Synopsys' Verilog Model Compiler (VMC) and is provided in a form that can be used by all SWIFT compatible simulators.

The timing model is a context-independent black box representation that provides a highly accurate complete view of the timing characteristics of the processor interface to the system chip. The timing model of the processor is created from the layout netlist using Synopsys' PrimeTime static-timing analysis tool. The timing model is provided in the open Liberty™ (.lib) library format and can be used by all commercially available EDA tools supporting Liberty. This model is used in the system-chip development for synthesis, timing-driven layout and static-timing analysis.

The test model enables test reuse at the SoC level by providing information on the test structures that have been implemented in the processor while protecting the IP contained within the design. The test model is created during the test-synthesis process using Synopsys’ DFT Compiler. The test model is represented using the Core Test Language (CTL) format and can be used by any EDA tools supporting the IEEE P1500 standard.

The physical model contains the physical characteristics of the processor for use in physical synthesis and layout of the system chip and is created by Astro as an abstraction in LEF format.

Together, these models provide all of the information required by the system designer to successfully integrate the ARM processor into a system chip.

ARM-Synopsys Reference Methodology – Complete Implementation Solution
The ARM-Synopsys Reference Methodology is a complete implementation solution for the hardening and modeling of synthesizable ARM IP. The methodology captures the set of best practices related to the hardening of the IP from RTL to GDSII as well as for the model creation process allowing the hardened IP to be deployed as a library level reusable component.

This methodology provides support for application specific hard IP that enables core- based design at the system level by providing the system -chip designer with a mechanism to rapidly port an ARM processor in soft form to an application-specific hard form that is very easy to deploy.

Moreover, the methodology provides a low-risk implementation process. This methodology has been developed jointly by Synopsys and ARM and validated at a number of ARM Licensees using different ARM processors and a variety of process technologies. This low-risk approach, coupled with the predictability and fast turn-around time, enables system designers to get ARM core-based products to market more quickly.

Research and development groups at both ARM and Synopsys are working together to solve problems at source that will result in higher quality IP, tools, and methodologies. The ARM-Synopsys Reference Methodology is an integral part of the standard IP distribution from ARM for all synthesizable microprocessors.

The ARM-Synopsys Reference Methodology supports the full range of ARM soft processors, including the ARM7TDMI-S™, the ARM7EJ-S™, the ARM966E-S™, the ARM946E-S™, the ARM926EJ-S™, the ARM1026EJ-S™, the ARM1136J-S™ and the ARM1136JF-S cores.

Trademark Information
ARM is a registered trademark of ARM Limited. ARM11 is a trademark of ARM Limited. “ARM” is used to represent ARM Holdings plc (LSE: ARM and Nasdaq: ARMHY); its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; and ARM Consulting (Shanghai) Co.Ltd. Design Compiler, DesignWare, Formality, Physical Compiler, PrimeTime, TetraMAX, VCS and Synopsys are registered trademarks of Synopsys, Inc. Astro, DC Ultra, DFT Compiler, Liberty and Power Compiler are trademarks of Synopsys, Inc.

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John Biggs has been involved with ARM developments since 1986 and co-founded ARM Ltd. in 1990. After a number of years working as a VLSI design engineer he went on to form ARM's Design Methodology Group in 1995. Biggs currently works as a Consultant Engineer in ARM's research group focussing on the development of advanced methodologies for the low-power deployment of synthesisable ARM IP.

Alan Gibbons is the IP Methodology Manager within the Solutions Group at Synopsys working with leading IP and semiconductor companies. Alan has spent more than 15 years in the design and development of ASICs and IP based SoCs for computer and communications-based applications.

©2003 Synopsys, Inc. Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other company and product names mentioned herein may be trademarks or registered trademarks of their respective owners and should be treated as such.