Increases in the average gate count of ASIC designs is forcing design teams to spend 20 percent to 50 percent of their ASIC development effort on test-related concerns to achieve good test coverage. Although it is considered good practice to follow design-for-test rules, grappling with embedded RAMs, multiple clock domains, reset lines and embedded intellectual property can have a significant impact on design schedules. Despite dealing with all that, 100 percent stuck-at fault coverage is rarely achieved. As a result, ASIC designs frequently enter production with less than 90 percent fault coverage, causing unnecessary device defect rates and board-level fallout.
The first step in inserting structures into a design for scan testing is to replace all flip-flops with scan flip-flops. Sometimes this is done as part of the synthesis process, although it is historically performed later in the flow. Inserting scan flip-flop s allows a higher degree of control of nodes within the design, thereby increasing the fault coverage. However, conventional scan technology does not provide for full control or observation of user nets in a design, leaving many structures untested.
The most common variety of scan flip-flop contains a multiplexer prior to the D input. This is so data can be shifted into the flip-flop during test mode or, alternately, a normal logic signal can be stored during user mode operation.
Conventional ASIC scan testing usually requires the following:
There is one test clock and the circuit must allow this to be applied to all scan flip-flops. During testing, all flip-flops are in test mode. During normal user operation, all flip-flops are in normal mode.
Notice that when using mux-based scan flip-flops, a multiplexer is normally inserted in the primary path for the user's clock to allow the test clock to be delivered to all flip-flops during test mode. All test flip-flops are placed in test mode at the same time.
Conventional test technologies require many design-for test (DFT) rules in order to provide enough fault coverage and acceptable device defect rates. (Fault coverage is a measure of what percentage of detectable stuck-at faults can actually be detected by a specific set of test patterns (vectors) on a particular design.) The result of not following DFT rules is that a number of faults can't be tested using conventional scan methodologies and the overall fault coverage suffers considerably.
To obtain reasonable coverage of detectable stuck-at faults using scan, a design typically must be fully synchronous. Hence we have the first DFT rule. Unfortunately, many designs-especially in networking and communications-require multiple asynchronous clocks, so it's impossible not to violate this rule. Also, in the quest for speed, synthesis often produces reconvergent redundant logic structures, another violation.
Commonly recognized DFT rule s include the following:
Designs should be fully synchronous with a common clock. Asynchronous inputs to storage elements must be disabled from an external pin during testing. Only sequential library elements specifically designed to support automatic test pattern generation may be used. Negative edge-triggered flip-flops are sometimes forbidden. Gated clocks are not allowed. They must be bypassed during test. Internal three-state buses should not be used; muxes are preferred. Combinatorial logic loops are not allowed. Reconvergent redundant logic is not allowed. External buses must be disabled during testing. Interfaces between IP blocks containing diverse test methodologies must be fully testable.
AutoTest was based on the premise that if all test-related circuitry is embedded in the base array, test-related matters could be removed from the ASIC development process. Embedded AutoTest circuits are not only defined independentl y from the user's design, but are fabricated before the user's design is known.
Since AutoTest is embedded in the underlying fabric of the ASIC, it is operated quite differently from conventional scan testing. While the scan test methodology used for conventional ASICs requires all scan flip-flops within a design to be in test mode at the same time, the sequence of operation for AutoTest will cause some modules to be in test mode while others are in normal mode during any specific test cycle. The function modules within an AutoTest ASIC contain both “control” and “observe” capability. This enables manufacturing to be tested by isolating individual modules and nets, fully validating the silicon integrity regardless of the user design implementation and regardless of DFT rules. To accomplish this, a new type of module is required. The unique Q_Cell within the module contains both “control” and “observe” capability and is also capable of being configured as combinational logic, flip-flops or RAM. This means that all nets can be controlled regardless of whether they represent clocks or sets/resets and whether or not they are part of redundant structures or combinational feedback loops.
A four-input mux-type cell (the P_Cell) is used for most combinational functions or combined with the Q_Cell for complex functions like full adders, while a high-drive three-state buffer is available for functions such as clock trees and data trees, as well as adding delay in circumstances such as automatically fixing hold-time violations (performed automatically in the physical layout flow).
AutoTest is not only capable of simultaneously capturing the state of all signals within the device, it is also capable of restoring that state such that the operation can begin from any arbitrary initial condition. Memories and flip-flops can be preloaded to emulate errors or unusual power-upstates. This capabilit y is useful for diagnosing problems in the field.
AutoTest is a combined software and hardware approach to test that eliminates all DFT rules and always provides 100 percent stuck-at fault coverage at the cell-pin level. Such coverage is becoming increasingly important as quality demands and device complexity increase. AutoTest has been used successfully in more than 100 structured ASIC designs, but its techniques could be implemented in standard cell ASIC designs as well.
Eric West is director of architecture at Lightspeed Semiconductor (Sunnyvale, Calif.).