Serial storage SoCs demanding to test

The advances afforded storage devices that use serial technology are significant. First, data throughput is increased: Desktop and mobile disk drives that support, for example, Serial ATA (SATA) interfaces can increase speeds from the shared 100 Mbytes per second (for parallel ATA) to dedicated bandwidth of 150 Mbytes/s or 300 Mbytes/s. In addition, serial interface cables are thinner than bulky parallel cables and use fewer pins, saving space in side the box.

This market transition comes at a time when hard-disk drive (HDD) manufacturers are under tremendous pressure to keep storage costs at a minimum; as price reductions in the PC market are pushed down the chain, consumers are conditioned to expect more storage capacity and speed for less money. In the last few years, these manufacturers have begun incorporating mixed-signal storage SoC solutions in their desktop and mobile HDDs. An HDD SoC combines previously discrete read-channel and hard-disk controller electronics and represents the single most important piece of silicon in a drive. This component controls the encoding and decoding of data from a storage platter, the storage and retrieval of data, and the speed at which the HDD can access data. The signal integrity enabled by HDD SoCs helps dictate the overall storage capacity of a drive, and innovations in these electronics are driving areal densities to 120 Gbytes per platter for desktop drives and 80 Gbytes for mobile.

Pr eserving signal integrity

The benefits inherent in SoC integration-improved board space, reduced power consumption and lower cost-are enhanced with the addition of on-chip high-speed serial interfacing, but design concerns must be addressed to ensure product performance and ease of testing. The read-channel IC within the SoC processes the electrical signals from the drive's preamplifier, so appropriate signal-integrity preservation measures must be taken in the design of, for example, an integrated SATA SoC to ensure that the high-speed signals from the SATA interface do not disturb the operation of the read channel. Likewise, the SATA signal transmitter and receiver are high-performance analog circuits that have to be carefully shielded from electrical noise.

The production volumes for these solutions are massive: A storage semiconductor provider will ship up to 5 million SoCs per month to any given HDD customer. Compounding this challenge is the value that HDD manufacturers place on red ucing defective parts per million; a failure rate of even 0.01 percent is unacceptable given the cost and time-to-market consequences of system or field failures.

Adding a native high-speed serial interface to this SoC builds on an already complex mixed-signal architecture and increases the challenges of silicon testing. The read channel and serial-interface portions of the solution are extremely analog-intensive, requiring a test methodology that must source complicated mathematically generated waveforms, accurately capture responses and then process them using digital signal processing. Juxtaposed against these analog test elements is the hard-disk controller portion, which requires traditional digital ASIC-type defect testing using digital vectors, at speeds that are cutting-edge for most automated test equipment (ATE).

One benefit of serial-interface SoC integration is that its low-voltage differential signaling is compatible with advanced semiconductor process technologies. This simplifi es design and supports high-volume manufacturing and production testing of storage SoCs, which are currently developed using 0.13-micron CMOS processing.

Multisite SoC testing is imperative to meet the high volumes and fast time-to-market mentioned earlier and to keep capital expenses in check. Using customized automated test equipment, these serialized SoCs are tested in batches of two or four and employ design-for-test methodologies, in which all segments of this mixed-signal solution (read channel, controller and serial interface functionality) are tested in parallel. In addition, the ATE must provide high-speed test stimulus and data capture as well as simultaneous processing of the output, which will be critical as the industry quickly moves to next-generation 3 Gbit/s parts.

This testing environment adheres to the cost-of-test business models for hard-disk-drive manufacturers and offers exceptional test throughput for high-quality, high-yield SoCs. Using these techniques, the high-speed serial-interfacing portion of the SoC can be accurately tested at a rate that is significantly below 1 second per part. This represents the benchmark across any industry developing serial-based solutions, where the current test times exceed 3 seconds per part.

The mechanics of the automated test fixture are also extremely important when testing these high-speed chips. Not only is it critical to get clean, deterministic and broadband signals to the IC under test, but also to ensure good electrical contact with the pads at wafer probe and pins at package test.

Contact resistance, load board characteristics, reflections, impedance match and crosstalk between signals can affect high-bandwidth analog signals used during SoC production testing.

These important matters must be addressed when designing the mechanical interface between the ATE and the probers/handlers and by appropriate design for testabi lity and observability during the design phase of the SoC.

Simply put, no other piece of silicon exists in the electronics industry to match the analog and digital complexity, high-volume requirements and price pressures of HDD SoCs. A high level of mixed-signal design expertise and production testing is required to ensure that SoC quality is not compromised.

However, the reward for proper production-testing efforts is a solution that minimizes the cost and maximizes the performance and reliability of a high-performance hard-disk drive.

Sandeep Kumar is director of test engineering and John Harris is senior product manager in Agere Systems Inc.'s Storage Division (Allentown, Pa.).