SoCs challenge production test methods

SoCs challenge production test methods
By Ron Wilson, EE Times
October 24, 2003 (1:12 p.m. EST)
URL: http://www.eetimes.com/story/OEG20031024S0026

Ironically, as the success of the system-on-chip has driven down direct silicon costs as a component of system cost, it has accentuated the very factor engineers are struggling to control: test cost. On one side, SoCs are becoming increasingly difficult-if not impossible-to test, and on the other side, test costs are in the spotlight as never before.

SoCs today have unimaginable transistor counts, and often have gone far beyond the old organization of CPU/scratchpad/I/O to include blocks that would be formidable standalone chips in their own rights. DSPs, ternary CAMs, gigabit MACs and advanced serdes blocks would each be a headache for test engineers all by themselves, and now they are showing up in multiples, all on the same die with CPUs and RAM.

Also, instead of one huge chunk of memory made as dense as possible, SoCs include dozens or hundreds of smaller memories of every conceivable shape, organization and function, some far too fa st to test directly at speed from off the die. This is forcing a revision of the old orthodoxy of memory testing.

Similarly, high-speed I/O has now emerged as a profound problem for testers. Multigigabit/second serial ports may run faster than any available tester, or even any available pin electronics. But loopbacks for self-test may not give an adequate view of the signals involved.

Now precision analog has climbed aboard, bringing with it all the as-yet-unresolved problems of analog test. And SoCs with on-board RF circuits-such things do exist today for undemanding standards like Bluetooth-can mean a rack of RF test gear custom-lashed to a beleaguered ATE system, and minutes of test-head time, with manual intervention.

If all this were not trouble enough, failure-analysis experts are warning of different failure modes from new processes. Don't focus entirely on stuck-at faults, they say. The dominant failure mode by 90 nanometers will be edge-rate and delay faults, often as transie nt manifestations of deeper signal integrity problems. At-speed testing will be essential.

What is certain is that the industry will be seeing a host of bright ideas to resolve all these problems. Some of them we offer in this week's contributed articles.