Until very recently, there were only two main digital integrated circuit (IC) implementation technologies: ASICs/ASSPs and FPGAs (where the former which we'll simply refer to as ASICs from here on in includes both standard cell and gate array-based devices).
The tradeoffs between these two technologies are well known. ASICs have huge NRE design and development costs, especially since the incredibly complex timing, power, and signal integrity effects we're seeing at today's process nodes require incredibly sophisticated (and expensive) design tools plus a huge amount of expertise.
A $1 million price tag for set of photo-masks for a 90nm device is not unknown, and the turnaround time from handing over the GDSII files to receiving working silicon is frustratingly long. Last but not least, once a design has been implemented as an ASIC it's effectively "frozen in silicon," and tweaking that design to accommodate any changes like evolvi ng and emerging communications protocols is time-consuming and expensive.
Of course the upside when using ASICs that these devices offer the best component densities (currently running somewhere around 110K equivalent gates per square millimeter), the highest performance, and the lowest power consumption. Furthermore, the per-unit cost of these devices is extremely attractive when you're aiming at large production runs of 100,000 to 1,000,000 parts or more.
And then we have FPGAs, the modern versions of which are also incredibly sophisticated. The NRE design and development costs associated with FPGA designs are a fraction of that of their ASIC counterparts. In many respects, complex deep submicron timing and signal integrity effects are hidden from the user, because they have already been addressed by the designers of the FPGA fabric itself.
FPGA design tools tend to be somewhat simpler and a lot cheaper than their ASIC cousins. Also, there are of course no photo-mask costs associated with an F PGA (from the perspective of the end user) and no device production delays. And tweaking the design to accommodate any last minute or ongoing changes is relatively fast and painless.
The downside when using FPGAs is that these devices offer relatively low component densities circa 1K equivalent gates per square millimeter (which is approximately 1 percent that of a standard cell ASIC). To some extent, this is because around 90 percent of the device is taken up by the programmable interconnect. In fact, the in-joke is that the FPGA vendors only sell us the interconnect and they throw in the logic gates for free.
FPGAs typically achieve only 20% the performance of high-performance designs and they consume 10x to 15x the power. Last but not least, the more sophisticated devices have high per-unit costs, which significantly impact their attraction for anything but prototyping applications or low production runs.
Enter the structured ASIC
The last few months have seen a flurry of activ ity by a range of ASIC vendors in a field that has only recently become generally referred to as "structured ASICs." The idea here is to create a component that fills the gap between standard cell ASICs and FPGAs.
In many cases the actual architectures of the various offerings are somewhat hard to pin down, because structured ASIC vendors are still largely working in "stealth mode." However, the underlying concept is to have a core element called a "tile" or "module" and to replicate this element across the face of the device. Different vendors augment this base architecture with various flavors of hard IP in the form of embedded RAM blocks and other functions.
Each vendor also offers its own selection of soft IP and firm IP, where the latter comes in the form of a library of high-level functions that have been optimally mapped, placed, and routed for that vendor's particular architecture. Furthermore, multiple global and local clock domains along with boundary scan (JTAG), full internal scan, and BIST are all typically pre-fabricated and embedded in the basic fabric.
Depending on the vendor, the core "tile" might contain some generic logic in the form of gates and/or multiplexers along with one or more flip-flops/latches. Alternatively, some architectures are based on tiles containing one or more lookup tables (LUTs) along with one or more flip-flops/latches.
But the one factor common to almost all structured ASIC architectures is that the majority of the metallization layers have already been pre-defined, such that the transistors in each tile have been pre-wired to implement the gates and/or multiplexers (or LUTs) and the flip-flops/latches. This leaves only a limited number of metallization layers to be created to connect the logic functions in the tiles (and/or to program any LUTs) and to link the tiles themselves into the local and global routing architecture.
As usual, tying things down to actual numbers is a little tricky, but the rumors on the street are that structured ASICs can achieve around 35% of the component density and 70% of the performance of their standard cell counterparts while dissipating only 2x to 3x the power. Furthermore, the development costs of structured ASICs are only 25% those of their standard cell equivalents, while the per-unit costs of structured ASICs are said to be only 10% of equivalent FPGAs (both of which make structured ASICs attractive for mid-range production runs). Last but not least, the reduced number of user-definable metallization layers dramatically cuts the costs of the photo-mask set and reduces the turnaround time to receiving working silicon.
ViASIC's single mask architecture
The great thing about electronics especially in the case of an idea like that of structured ASICs is that there are so many different possibilities to play with. One unique offering comes from the folks at ViASIC who have a via-programmable device that requires the customization of only a single via l ayer between metallization layers 3 and 4.
Unlike a typical ASIC in which adjacent metallization layers alternate between the north-south and east-west directions, the tracks on ViASIC's metallization layers 3 and 4 toggle back and forth between directions. Meanwhile metallization layers 1 and 2 are used to establish the core functions (and to implement any RAM), while layers 5 and 6 provide long track segments across the device (again, the customizable via layer is used to link into these global tracks).
Another feature of ViASIC's architecture is that it uses the concept of a "base tile" containing only generic logic in the form of prefabricated gates and multiplexers. An array of these base tiles are then combined with special tiles containing registers, RAM, and other logic to form a "master tile." Finally, an array (sea) of these master tiles is prefabricated across the face of the chip.
The guys and gals at ViASIC claim a number of advantages to their approach, not the least that having a s ingle customizable via layer cuts photo-mask costs and turnaround times to a minimum. The interleaving of the RAM and logic by means of the hierarchical base/master tile concept allows ViASIC to achieve very respectable component densities around 100K equivalent gates per square millimeter. And then there's the fact that the individual pre-defined track segments can be pre-characterized at a high level of accuracy with respect to resistive, capacitive, and inductive parasitics and timing and signal integrity issues.
Structured ASICs are still an emerging field, and it's going to be really interesting to see how things develop over the coming months. One area that requires close attention is that of the tools used to design these devices. It seems that many structured ASIC vendors are desperately trying to use existing ASIC tools as a stop-gap measure while they wait for something better to come along.
However, playing tricks like restricting the router to only use a subset of metallization layers almost certainly results in less than optimal results. This may leave the field open for small and startup EDA companies to provide unique offerings in this area (particularly for something as radically different as ViASIC's single customizable via layer).
In the case of synthesis, FPGA-specific tools like those from Synplicity are of interest in the structured ASIC realm, because these are already geared toward mapping functions into programmable blocks and working in a hierarchical "logic cell slice logic block" type environment.
Of particular interest is the use of hybrid devices that currently start life as standard cell ASICs containing FPGA cores. In this case, the design tools and design flows for the main body of the ASIC as compared to the FPGA core are disparate to say the least. However, once structured ASIC-specific design tools come online, it may be possible to use common tools and similar (or at leas t related) flows for the ASIC and FPGA core portions of the design.
Of course nothing is certain in this industry, and new concepts and components tend to leap onto center stage with a fanfare of trumpets and then evaporate into nothingness as soon as one's back is turned. But I have a feeling that structured ASICs are here to stay with us for a while, and that vendors like ViASIC are going to delight us with a positive plethora of new architectures and cunning concepts for years to come. So it's an official "Cool Beans" for ViASIC from me. Until next time, have a good one!
Clive (Max) Maxfield is president of Techbites Interactive, a marketing consultancy firm specializing in high-tech. Author of Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and co-author of EDA: Where Electronics Begins, Max w as once referred to as a "semiconductor design expert" by someone famous who wasn't prompted, coerced, or remunerated in any way.