Three-dimensional SoCs perform for future

Aside from high development costs and long design cycles, a conventional two-dimensional SoC poses a litany of challenges, not the least of which is integration of two or more incongruent functional blocks with a single process technology. In a traditional SoC approach, designers cannot simultaneously optimize digital, analog, memory and I/O. Smaller feature sizes make these critical components increasingly less com patible. The least-common-denominator methodology results in unfavorable performance and cost trade-offs.

In a 2-D approach, configuration changes and component upgrades are lengthy and costly endeavors. The need for more memory is growing faster than the need for more processing power, but the ability to achieve greater density is growing more elusive.

Yet demand trends in cellular, wireless LANs and high-volume consumer applications drive the need for simultaneous improvements in integration density, form factor, power consumption and performance-so there must be a way to achieve this beyond status quo methods of multichip packaging or even discrete implementation.

Vertical or three-dimensional integration technologies allow the individual functional blocks of an SoC to be built in the process technology that optimizes their individual cost and performance. An SoC is the sum of its individual parts and if analog, logic, memory and I/O are individually optimized, then overall system performance and cost can be optimized.

Foundry-based, 3-D integration achieves the integration density and performance to meet future market demands. Three-dimensional SoCs can be built using proven, off-the-shelf components. Selective die-to-wafer bonding and 3-D interconnect technologies allow designers to achieve SoC results from a system-in-package level of effort. And unlike packaging solutions, foundry-based integration delivers the downstream, wafer-scale cost benefits that result from wafer size increase or feature size shrink. This is a compelling alternative to conventional methods for 2-D SoC design and multichip packaging.

With the development of EDA tools and key standards for 3-D circuit design, the industry can fully benefit from the density, power reduction and performance benefits that this new technology can deliver.

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