In data networking, speed and bit error rate (BER) are the rulers by which silicon providers are measured. Serializer/deserializers-whether standalone application-specific standard products, commodity devices or integrated ASIC links surrounded by 8 million to 20 million gates of proprietary logic-are the primary tools for attacking both sides of the equation.
Network infrastructure customers must get more bandwidth out of current deployments because they no longer can afford forklift upgrades. The backplanes stay put, and customers rely on line card upgrades to increase performance.
Serdes providers thus must craft devices that can operate within the confines of systems that were defined three to five years ago to handle 622 Mbits/second to 1.25 Gbits/s but that now must accommodate 3.125 to 3.75 Gbits/s typical-and sometimes more than 5 Gbits/s-at both ends of the link.
At the same time, greater numbers of intellectual-pro perty (IP) providers are designing and releasing serdes cores that customer-owned-tooling users integrate into fab libraries.
Such cores address a multitude of system-design areas. Front-plane devices on the line cards need to be standards-compliant for plug-and-play interfaces, such as FC1/FC2 and Sonet, or for chip-to-chip interfaces from a range of vendors. At the extreme of system requirements might lie a backplane interface where the device must run across two line cards, two mating connectors and 40 inches of FR4 but still achieve a 0 BER at 1E-17 for the system.
As customers made the transition from 2.5 to 3.125 Gbits/s, they discovered that system-level parameters played a huge role in whether they could achieve error-free systems. They also found out that even within the same system, serdes from different vendors may act differently. Having a strong serdes circuit design is not enough, since not all serdes are created equal.
Equipment makers are increasingly looking to silico n providers that have taken a "pins out" view of the system before tapeout of the design to ensure first-pass success. The modern chip supplier must have a good understanding of board fabrication, partner with connector and cable providers to determine what will and won't work under certain conditions, and consider all the system-level obstacles the design might confront.
All parties involved in IP and system development must partner early in the process. The ASIC customer who ignores system issues at high data rates does so at his peril.Steve Spencer is a member of the technical staff at Texas Instruments Inc.