Designing with hard power constraints
By Juan Antonio Carballo, EE Times
January 15, 2004 (5:38 p.m. EST)
In high-performance 90-nanometer designs that are communications-intensive, power has become a hard constraint, and not just in battery-powered devices. High-performance computing chips, broadband processors and networking silicon simply cannot consume more than a certain amount of watts, given the packaging options and energy dissipation characteristics of the system in which they are embedded.
Several trends are compounding this problem. First, leakage power has officially become a first-class component. It can easily exceed a third of total power even for high-activity designs. Although high-performance designs can tolerate more leakage than battery-powered designs, there is a point at which chip yield is leakage-limited. Second, increasing per-chip bandwidth requirements make the power problem more difficult, as communications tend to include large amounts of analog-type components and are often difficult to turn off. Finally, there is a trend toward consolidating design teams, and thus a need to cover an increasingly broad set of requirements (for example, communications standards), which can easily result in a single, energy-inefficient design.
Logic and circuit optimization methods need to adapt to simultaneous speed- and power-constrained design. For practical reasons they must be smoothly integrated in an ASIC-style methodology, since even processor designs increasingly rely on synthesis-based methods. The 90-nm logic optimization loop has no choice but to tightly integrate power and timing loops. Fortunately, the logic optimization arsenal includes some powerful levers:
- Increased library design space. Libraries including multiple-threshold devices are used in the standard flow, and the number of thresholds in the transistor menu is increasing. Using three thresholds helps meet power constraints (with high or standard thresholds) while achieving the required performance (with low-threshold cells in critical paths) . Synthesis, timing and power tools need to seamlessly mix and match libraries with these devices. Given the possible device combinations, special care is put on managing process corners.
- Explicit leakage management. Leakage must be accounted for during timing and power optimization. The design methodology must include cell-usage monitoring and guidance to limit the amount of low-threshold or other leakage-producing devices. Leakage estimation tools are used during early logic design and more accurate leakage analysis runs can be performed on synthesized blocks during logic optimization.
- Increased supply space. Although overall power still depends strongly on the supply level, lowering global supplies in 90 nm and below is difficult. As a result, selectively applying multiple supplies to different design blocks may be very useful and sometimes critical. Thus timing and power optimization need to run smoothly on blocks crossing multiple-supply boundaries as level-shifting cells are transparently ins erted in the logic.
- Adaptable logic. Sharing logic across many applications is cost-effective but often leads to inefficient designs that cannot meet power constraints. Fortunately, each application tends to cover only a portion of the function-frequency-voltage space. Making logic adaptable enables a power-constrained yet resource-efficient design. Examples include multiple selectable internal clock rates, state machine configurations and bandwidth connections, even within a single, reusable core. Measure-and-adjust techniques can be used if ease of use is fundamental.
Despite the move to higher abstraction levels, circuit design takes on a renewed importance as power increasingly depends on circuit and technology choices. Fortunately, some powerful circuit optimization methods are available:
- Transparent cell customization. New logic families that "look" like static logic to the methodology and use standard clocking are especially attractive. An efficient cell characte rization flow is proving to be fundamental so that these cells can quickly be added using the same procedure as conventional standard cells.
- Circuit leakage optimization. Leakage-optimized cells are most desirable when optimizing low-switching logic. For these cells, logic families that are fundamentally superior in leakage are preferred. Circuit tuner tools need to explicitly account for leakage. Additionally, body bias control and header and footer usage are subject to intensive circuit analysis.
- Digitalization. Constant-current biases, low-voltage headroom and large, numerous transistors in differential architectures make mixed-signal circuits a large part of the power budget. Transforming analog-style cells into digital-like cells is an attractive approach to circuit optimization, especially in circuits at the mixed-signal boundary. But digital-style circuits may hold some unwanted features, such as high supply sensitivity, and thus are used only when higher-level analysis proves them acceptabl e.
- Explicit signal-integrity management. Power grid analysis tools have become a permanent fixture of the flow. Strict power grid analysis needs to be performed as an integral part of the standard-cell characterization flow, with signal-integrity information a primary output of this flow.
Juan Antonio Carballo is research staff member at IBM Research (Austin, Texas).
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