by Dr. Yervant Zorian and Dr. Mouli Chandramouli, Virage Logic
Every new generation of semiconductor technology delivers the advantage of higher levels of integration and performance, providing advanced capabilities in a multitude of electronic applications. However, the shrinking geometries of 0.13 micron and below in deep submicron technologies make such devices more susceptible to new yield-limiting defects that impact conventional semiconductor manufacturing operations.
The existing external infrastructure including ATE and associated equipment is not necessarily capable of coping with the new defect levels in terms of detection, isolation, diagnosis, and yield-optimization solutions. This limitation has slowed down the widespread deployment of system-on-a-chip (SOC) designs. To deliver high-volume products, the nanometer technologies require more than external infrastructure.
As a result, we see a need for on-chip support infrastructure to tackle these manufacturability issues. To address this challenge, semiconductor intellectual property (IP) providers have introduced embedded IP blocks called infrastructure IP (IIP), and designers have incorporated these IIP blocks into SOC designs. The IIPs supply a range of test, diagnosis, and repair capabilities throughout the life cycle of the device.
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