In the 1990s, wireless technologies developed in a way that can best be described as unbelievable. Consequently, the number of mobile subscribers has grown more than a hundredfold in the past 10 years. There are over 1 billion subscribers globally, and the number is growing at a healthy pace.
Radio systems continue to develop from the current second-generation and evolved-2G systems toward higher data rates and better mobility. While the third-generation cellular system is being rolled out and the first terminals have hit the shops in Japan and Europe, standardization work continues toward even higher data rates.
Rising data rates bring attendant increases in processing-power requirements and complexity. Today, it is not only computational power that limits the performance of baseband ASICs that include a processor core or cores; on-chip communication, line delays and clock distribution are also factors. To reduce the load from the processing cores, decentralized architectures are being considered in which small controller processors or units running at low frequencies can be distributed within the engine. With multiple processors, management of the processing-power resources becomes a key challenge.
An alternative approach for optimizing the baseband is to use configurable logic, configurable processors or processor generators. These provide more freedom in optimizing the trade-off between performance and flexibility. Still, because of the exploding baseband complexity of cellular platforms, the main challenges have to do with design methodology, verification and testability.
In the RF domain, digital CMOS technology has been the hottest topic in recent years. The technology has also proven to be applicable for the RF but poses several disadvantages compared with the widely used RF BiCMOS. In particular, substrate-coupling effects are stronger, and the quality of transistor models is not at a sufficiently mature level for first-time success in RF IC design. The cost calculation of RF CMOS reveals that a one-to-one replacement of the RF circuit with a CMOS version provides only a marginal, if any, cost benefit. The calculation changes immediately when large digital content, such as digital filtering and control logic, is integrated on the same chip.
To fully exploit the speed of the latest digital CMOS technology in RF, completely new circuits and architectures must be invented. In contrast to just mapping the traditional RF circuits to CMOS, the new architectures should be based on fast sampling and time-discrete signal processing. That blurs the interface between the RF and baseband, and it can dramatically improve the portability of the RF front end to future CMOS process nodes.
Whether this will be the next cornerstone in the architectural development paving the way to true single-chip radios is not yet known. In any case, these new digital radios will establish even more pressure for developing better system- and behavioral-modeling tools for complete engine optimization.
Given the wide variety of radio system platforms, terminals offering access to several systems are required. Access to all available systems-multiband GSM, wideband CDMA, cdma2000, Bluetooth, FM radio, GPS and wireless LANs-is technically feasible. In practice, two main questions about multiradios have yet to be answered: For which combinations of systems can radios be integrated at a reasonable cost and size? And which combinations make sense in the marketplace?
In the baseband domain, the required functions for the various radio standards are so much alike that today's baseband already has the capability for multiradio processing. Because of the different air interface specifications, the RF section of a multiradio can easily become very complex, with a large number of parallel circuit blocks. In multistandard or multiband RF ICs, the programmability of circuit blocks can be exploite d to reduce complexity and silicon area.
Multiradios also introduce miniaturization challenges to the antennas and front-end filters. The antennas need to be designed as compact multisystem antenna modules, and filter miniaturization is crucial. Bulk-acoustic-wave technology is one key enabler for filter miniaturization. Microelectromechanical systems technology still requires proof for RF applications.
In the future, because of multistandard communication and multimedia applications, platforms will be more complicated. Part of that complexity will come from higher data rates within wireless-access devices, displays and cameras. Interfaces must be standardized to cope with the complexity and enable a large variety of hardware extensions.
Future challenges include maintaining 10 percent annual growth in battery capacity and handling hot spots in highly integrated engines. As we know, the number of components will decrease continuously, as traditional chips evolve into systems-on-chip and as components become modules or systems-in-package. Finally, system complexity is increasing so much that better system-level design tools are needed to optimize and verify the designs and to test the hardware.
There are many potential methods and technologies to tackle the increasing complexity of handheld systems. One of them is standardization of the core areas of the platforms, such as an operating system like Symbian.
Another example is related to the linkage among wireless-access, application-engine and user-interface hardware. Thus far, this linkage has been based on dedicated solutions. A more generic interface must be standardized to easily attach new components into the system. The Mobile Industry Processor Interface (MIPI) Alliance has been launched to address this challenge.
Since complex systems comprise an enormous amount of parameters and dependencies that must be optimized, advanced EDA tools are needed to support product development. Tools are enablers for faster time-to-market and are boosters of evolution. Achievements in embedding, miniaturization, power savings or design verification depend strongly on tools. The top-down design flows currently available have weak spots that require too much effort and orientation from designers.
Today's multilevel requirements include C-code, VHDL and transistor-level descriptions as well as traditional, mixed-signal-based environments. A better framework is needed to fully enable utilization of intellectual-property blocks in integrated-circuit design.
Standardized data transmission formats (cf. GDSII) need to be created to transfer information from one tool to another. Ease of use is a must. For example, library translations should not be visible to a designer. Collaboration between technology and EDA tool houses is needed to provide seamless, reliable and tested design environments.
To make significant strides in embedding, more effort is still needed to develop practical substrate-noise-modeling tools .
Cross-technology modeling like 3-D package modeling combined with RF IC simulations must be supported, which is extremely important for chip modules or stacking. Removing overhead from digital-domain designs, for example, requires better support for optimizing the hardware/software partitioning. In some areas, such as antenna design, the tools are in good shape, but new, more powerful and flexible simulation algorithms should be developed.
To achieve the best performance in handheld devices, any overhead in the system must be eliminated. Therefore, adaptive solutions are required. For example, in baseband platforms, dynamic voltage and frequency scaling, digital technologies to tackle leakage current, digital architectures applying asynchronous structures and usage of reconfigurable circuits should be applied. All possible means for preventing unnecessary switching in digital circuits and overhead in latencies need to be applied.
Flexibility will be key in the ability to implement a ll those numerous product categories in the future, since they cannot be based on one or two platforms. As a part of this strategy, enormous ASICs may not be the most probable choice, because they can be too expensive and more difficult to test. In addition to flexibility, power consumption, cost and time-to-market are important drivers. Whatever techniques are applied, the total cost of the product must be reasonable.
Yrjo Neuvo is executive vice president, CTO, at Nokia Mobile Phones (Espoo, Finland).
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