10GBASE-T PHYs Pose Challenges to Designers
Joseph Babanezhad, Plato Labs
Feb 25, 2004 (6:00 AM)
Figure 1: Diagram showing the carious elements used to characterize copper cables.
A 10GBASE-T physical layer (PHY), previously thought to be unachievable, is the next generation of transceivers that can run over unshielded twisted-pair (UTP) cable. It will provide the low-cost alternative to 10-Gbit/s transceivers that run either over fiber optics or Infiniband cabling.
Designing and manufacturing a 10GBASE-T PHY, however, is significantly more complex and costly than a 1000BASE-T PHY. Initially the implementation of the 10GBASE-T PHY device is estimated to require an approximate complexity of 1.5 times the currently available quad 1000BASE-T chip.2
In this article, we'll look at the implementation options that designers are using today to develop 10GBASE-T systems and the challenges this design approach provides. We'll then explore a proposed alternate approach and it's impact on PHY design.
Every UTP cable consists of four wire pairs. A UTP cable typically is characterized by insertions loss (attenuation), return loss (in turn causes echo on the line) and crosstalk (Figure 1). Crosstalk is of particular importance.
There are different flavors of crosstalk to consider on a UTP line. Near-end (NEXT) and far-end (FEXT) crosstalk are caused by the interactions of different wire-pairs inside the same cable. Alien cross talk (ANEXT), on the other hand, is caused by other unrelated cables.
In datacom designs, the PHY provides the interface between the cable (channel) on one side and the media access control (MAC) layer (digital "1" and "0") on the other. Most of the channel impairments can be cancelled in the PHY since the sources of these impairments are accessible.
ANEXT, on the contrary, acts as a frequency dependent background noise. While some mitigation techniques, such as using more sophisticated patch cords or unbundling otherwise bundled cables, can be applied to the existing cable plant, it is generally believed that ANEXT cannot be cancelled at the PHY.
In order to deliver a 10-Gbit connection over 100 m of UTP CAT6 cable for example, a 10GBASE-T PHY has to implement 65 dB of echo, 50 dB of NEXT, and 50 dB of FEXT cancellations. Under these conditions the capacity of the channel, consisting of two 10GBASE-T PHYs and the 100 m of UTP CAT6 cable, is marginally below the Shannon limit (17.77 Gbit/s).3
Classic PHY Architecture
Figure 2 shows how a traditional dual 10GBASE-T PHY node connects to the UTP cable. It also shows how various signal sources give rise to various types of impairments.
Figure 2: Diagram showing how a 10GE PHY connects to a Cat6 cable.
As seen in Figure 2, each PHY consists of four unit transceivers each connecting to one of the four pairs of the UTP cable. The transmit and receive signals of a given unit transceiver are combined and sent on the same wire-pair by means of the hybrid circuit.
Under a classic method, the unit transceivers are implemented using analog front-end (AFE) and digital signal processing (DSP) blocks. In this architecture, the AFE implements some basic signal processing tasks which consist of filtering, programmable-gain and analog-to-digital conversion. The DSP portion, on the other hand, implements all the signal/impairment restoration/cancellation such as equalization, echo/crosstalk cancellation mentioned above.
In order to transmit and receive 10-Gbit/s over 100 m of CAT5e/6 UTP cable with a bit error rate (BER) of 10-12 the DSP needs to perform 10 teraops. The use of a multiple-input, multiple-output (MIMO) processing element allows massive reuse of computing resources. This significantly reduces the overall needed teraops.4
More over, the AFE (after filtering and gaining the receive signal) needs to sample the receive signal from the UTP cable with 11 effective number of bits (ENOB) of amplitude accuracy and 100 fs (10-13) of timing accuracy.5 Depending on the type of line-signaling used, the analog-to-digital converter's (ADC's) sampling frequency can vary from 833-to-1250 MSample/s.
While very few stand-alone ADCs (mostly in SiGe process) have been developed to achieve ENOB=10 at sampling frequencies close to 1 GSample/s, a survey of last 5 years of presentations at International Solid-State Circuit Conference (ISSCC) does not reveal commercially available CMOS counterparts of these ADCs. Moreover, assuming by some stretch of imagination, when these ADCs do become available in CMOS technology, integrating four of these ADCs on a an ULSI chip along with massive amount of digital circuitry clocking at gigahertz frequencies encounters another fundamental problem';signal-to-noise ratio (SNR)
As Figure 3 shows the overall SNR of an ADC, in turn defined by its ENOB, is a function of signal bandwidth and the jitter of the sampling clock.6 This gives rise to ADC's jitter-limited bandwidth phenomenon. As an example the SNR (ENOB) of an ideal ADC measuring a signal with a bandwidth of 625 MHz and 1-ps rms clock jitter is limited to 43.9 dB (7 bits).
Figure 3: SNR of an ADC used in the front-end of a 10GBASE-T design.
Alternative PHY Appraoch
A proposal to the IEEE 802 committee5 details a more efficient architecture for implementing the 10GBASE-T PHY. In this architecture, the AFE implements the primitive tasks mentioned in the previous section as well as part of the signal/impairment restoration/cancellation task such as echo and NEXT cancellation. In fact, this technique has been previously used in demanding high data-rate read channels.7
A major advantage of the proposed approach is that it prevents the ADC quantization noise boosting that otherwise results when the AFE implements only the simple tasks mentioned in the previous section.
Figure 4 shows the application of the proposed AFE in a 1000BASE-T AFE. In the top trace, a simple AFE is depicted that only implements the primitive tasks mentioned before. The total task of signal/impairment restoration/cancellation is relegated to the DSP portion. Simulations show that ADC's quantization noise is boosted by a factor of 6.68. The SNR at the input to Viterbi decoder is 18 dB.
Figure 4: Comparison of the traditional (top) versus alterative (bottom) Gigabit Ethernet PHY architectures.
In the bottom trace the AFE, in addition to the primitive tasks, implements part of the signal/impairment restoration/cancellation task. Here, primarily due to the lack of ADC quantization noise boost, SNR at the input to Viterbi decoder improves to 19.72 dB.
The implementation of a 10GBASE-T PHY chip in a commercially available CMOS process requires a significant amount of innovation in communication theory, analog mixed-signal design. and DSP design. The application of a 10GBASE-T PHY over the existing UTP cabling would require the use of some mitigation techniques towards reducing the adverse effects of ANEXT. A mostly DSP solution will severely tax the state-of-the-art ADC capabilities. A solution, as shown above, is to have AFE implement significant signal/impairment restoration/cancellation tasks to reduce the burden on ADC. References
- Alan Flatman, "Installed CablingForecast to 2005" IEEE 10GBASE-T SG Vancouver Jan. 2003. http://www.ieee802.org/3/10GBT/public/jan03/flatman_1_0103.pdf
- 5 Criteria, IEEE 10GBASE-T SG July 2003 meeting San Francisco. http://www.ieee802.org/3/10GBT/public/jul03/5Criteria_1_0703.pdf
- Joseph N. Babanezhad, "10GBASE-T Line Signaling". IEEE 10GBASE-T SG Dallas March 2003. http://www.ieee802.org/3/10GBT/public/mar03/babanezhad_1_0303.pdf
- G. Zimmerman and W. Jones, "10GBASE-T Ttorial", IEEE 802.3 Kauai, Nov. 2002. http://www.ieee802.org/3/tutorial/nov02/tutorial_1_1102.pdf
- R. Spencer, "Analog Font Ends for Ethernet on Copper", IEEE 10GBASE-T SG. San Francisco. July 2003. http://www.ieee802.org/3/10GBT/public/jul03/spencer_1_0703.pdf
- B. Brannon and C. Cloninger, "Redefining the Role of ADC in Wireless", Applied Microwave & Wireless, March 2001.
- D. Chunkai Wei et al, "A 300 MHz Mixed-Signal FDTS/DFE Disk Read Channel in 0.6-μm CMOS", ISSCC pp.186-187, San Francisco, Feb. 2001.
About the Author
Joseph N. Babanezhad is the co-founder and CTO of Plato Labs. Joseph can be reached at email@example.com.
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