| SAN JOSE, Calif. — Experts painted a stark picture of the state of verfication of reused semiconductor IP at the DVCon show here on Wednesday (March 3). |
The panel chaired by Cadence chief architect Ted Vucurevich also offered a variety of possible improvements. "We know that a typical 90-nm SoC design done from scratch is going to cost the design team $25 million," Vucurevich said. "There is growing agreement that 70 percent of that money will be spent on verification — not just functional verification, but verification in all of its aspects.
"Today, the only effective way to reduce the overall cost is design reuse. But what we don't know is how to deal with that 70 percent of the job, the verification, when it comes to verifying IP from an outside source. How are we to verify IP that we reuse?"
Iwashita of Fujitsu Laboratories, underlined the severity of the problem. "Today, past use is the only measure we have of IP quality," Iwashita lamented. "But it is not sufficient. The fact that the IP was made to work in one design is no proof that it will work in another."
Iwashita said the design community must progress from circumstantial evidence to formal descriptions of IP function and to accurate coverage metrics for verification. He went on to describe a program in which Fujitsu used documentation on interface IP to extract a formal, executable specification in the form of a finite state machine. This model was used to evaluate the IP, its documentation and the test bench provided with it.
"We have found errors in important third-party IP. We have found errors in the documentation for the IP. And we have found that IP vendors' test benches can provide less than 50 percent test coverage,'' Iwashita said.
Bernard Deadman of Structured Design Verification Inc. said inter-block connections tend to be either via a standard bus protocol or a proprietary point-to-point link. "The most problematic links have been the latter, because they are proprietary and not always well documented," Deadman said. "But if you look at the standards for on-chip busses, you find that they are like quicksand: They look solid but they won't support weight."
Michael Beaver of iReady said several of its recent designs depended heavily on IP reuse. "Know your own features and constraints" as the starting point for both selecting and verifying IP, he said. Beaver suggested using the design features and constraints to construct a spreadsheet with evaluation and verification points, both to use as an evaluation guide and as a communications tool between the design team and the IP vendor.
Beaver also warned, "Today, most soft IP is not hard-coded, it is generated using your configuration input. The code that comes out is different for every configuration. That nullifies most of what we have achieved in defining IP quality metrics."
Bob Fredieu of Zaiq Technologies addressed the question of verification IP itself. "The market is not working well for verification IP," Fredieu said. "It is hard to find, hard to evaluate and most of it isn't very good."