The trend toward integration of analog and digital functions in the wireless infrastructure market has intensified over the last five years, as integration is viewed as the best way to reduce overall system cost and size. From a marketing and end-customer standpoint this is an ideal solution, but the challenges it presents to analog and digital design engineers are substantial. One example of such integration is the AD6650 IF-to-baseband narrowband receiver, which incorporates many analog and digital functions on a single die. Throughout the design and verification process design engineers had to overcome many hurdles to make this product a reality.
The first challenge for the design team was to develop an understanding of the complete-system level. To bypass this step would mean a substantial risk of under- or over-designing the final product. If under-designed, it would not pass the end customer's system requirements; and if over-designed, the size and cost of the end product would be impacted, thus defeating the whole purpose of integration. So before the first transistor was designed, a thorough system study was initiated. This paid big dividends in the final evaluation phase, which included conducting bit error rate (BER) measurements to validate the product in a system environment.
Once the system requirements were fully understood, the design process could begin. Analog designers traditionally use Spice simulations to design and validate their core blocks, while digital designers use Verilog for this same purpose. Throughout the design process both design teams collaborated on defining interaction between the analog and digital blocks, leading to the most difficult challenge of putting the blocks together and functionally simulating the overall chip.
Although many functional blocks depended on both analog and digital designs, one of the most challenging to simulate was the automatic gain control (AGC) loop. The programmable AGC loop monitors the input power to the device and increases or decreases the front-end gain to optimize the part's dynamic range. For the loop to operate correctly, both analog and digital techniques are employed to monitor the input power. To functionally simulate this loop, the design teams worked closely with the computer-aided design (CAD) team to develop a solution for the two very different design tools to communicate. This co-simulation tool allowed Spice to call the Verilog modules, much like a software program calls an external library (commonly called a .dll). With the ability to co-simulate, it was possible to fully exercise and verify the proper functionality of this loop prior to silicon fabrication.
It is essential to consider the validation process during the design process. A board-level designer will traditionally verify each block individually. For an analog-to-digital converter (ADC), this means looking at figures of merit like signal-to-noise ratio (SNR) and spurious-free dynamic-range (SFDR). For an amplifier the figures of merit include Input Intercept Points IIP3 and IIP2. With everything integrated, however, it would be impossible to evaluate the performance of each individual device, unless special provisions were made during the design process. The key to solving this problem for the AD6650 was adding a test bus that allows direct access to the high-performance on-chip ADC. Digital test registers enable this bus, allowing the ADC to evaluate the gain response, IIP2 and IIP3 of the video graphics array (VGA), the passband of the low-pass filters, and the phase and amplitude imbalance of the quadrature mixer. This test bus was essential in the initial evaluation of the product but could easily be shut down when the evaluation was complete.
As mentioned above, the final stage is to verify that the chip fully complies with all requirements in a system-level environment. This type of testing has traditionally been conducted by the end user. However, the increasing complexity of integrated devices and the decrease in available end-user resources have pushed this responsibility toward the semiconductor designers. In this particular case, this meant verifying that the product complied with the GSM/Edge test specification. This specification stipulates a full battery of tests such as minimum sensitivity under static and dynamic conditions, blocking/interferer tests, and many others.
| A traditional receiver has many standalone ICs that are evaluated individually. This baseband narrowband receiver for GSM/Edge replaces up to 11 of these discrete components and thus must be designed and evaluated at the system level. |
Source: Analog Devices Inc.
These tests are conducted by passing a GMSK (GSM), or 8-PSK (Edge) signal of varying amplitude through the device under test, and then through an equalizer. The data at the output of the equalizer is compared with the transmitted data to determine if any errors occurred. From this output the bit-error rate is calculated. Passing these strict tests not only serves as the final verification step, but also helps gain the confidence of the end customer.
Anticipation of, and creative solutions to, the design challenges presented by systems-on-chip provide the end customer with a solution that is smaller and lower cost, and one that is fully simulated and tested. As a result, the overall system design cycle for basestation manufacturers is completed sooner and with fewer board iterations. These benefits suggest that the drive to integrate in wireless infrastructure will continue to intensify.
Chris Cloninger (email@example.com) is a systems applications engineer in the Wireless Infrastructure Products Division of Analog Devices Inc. (Wilmington, Mass.).