Tutorial on Designing Delta-Sigma Modulators: Part 2
Mingliang Liu, Extron Electronics
Apr 01, 2004 (6:00 AM)
Figure 7: Diagram of a typical third-order delta-sigma modulator.
The transition from second-generation (2G) to third-generation (3G) wireless cellular systems requires multi-standard adaptability in a wireless receiver. An important answer to this request is the use of delta-sigma modulators for IF-to-baseband conversion, which will satisfy the dynamic range requirements for aggressive digital signal processing, and at the same time, add adaptability and programmability to the characteristics of a RF receiver.
This articles addresses the issues of how to design effective delta-sigma modulators for wireless receivers that need to support GSM, DECT, and wideband CDMA (W-CDMA) operation. A single-loop third-order modulator topology suitable for low power and high integration multi-standard receiver is described.1 The trade-offs in the modulator design are also presented and explained.
In Part 1 of this article, we compared today's typical receiver architectures to the delta-sigma modulator approach. We'll also provide a look at the different types of delta-sigma modulators available and the key elements that make up a modulator designs. Now in Part 2, we'll further the discussion by looking at circuit implementation issues as well as the key sub-elements that make up a delta-sigma converter design. We'll also provide some simulation results as well as future design work that needs to be conducted in this space.
The key circuit-level building blocks of the proposed third-order delta-sigma modulator, are shown in Figure 7. They include switched-capacitor integrators, operational transconductance amplifiers (OTA), a single-bit quantizer (a latched comparator followed by a static SR latch), and a clock generator.
The three integrators and the comparator are controlled by two-phase, non-overlapping clocks, ck1 and ck2; an early clock phase ck1e to strobe the latched comparator; two delayed clock phases, ck1d and ck2d; and complements of the delayed phases, ck1db and ck2db.
The first integrator is shown in Figure 8.
Figure 8: The first integrator of a third-order delta-sigma modulator.
During ck1, the input voltage is sampling onto CSampling. During ck2, charge proportional to the difference between V_i and DAC reference voltage, V_ref, is transferred from CSampling to CIntegrating.
The sampling and integrating capacitances are shown in Figure 8. The sizing of these switches obeys to the analysis pattern described in chapter 4 of Reference 1, where NMOS switch's W/L ratio is at least 20/1, and the minimum PMOS switch's W/L ratio is 40/1.
The delayed clock phases ck1d and ck2d reduce signal-dependent charge injection from switches S_3 and S_4 onto CSampling and CIntegrating. S_5 resets the integrating capacitors during power-on or the transformation from one standard to another. In addition, it also serves as clipper for the integrator output voltages at high swing, which is often referred to as the integrator reset approach for modulator stability.
The second integrator is shown in Figure 9. The additional feedback branch, which creates the local resonator in the case of W-CDMA, is controlled by the enable signal, en_wcdma and ck1d, through a MOS AND gate.
Figure 9: Second integrator of a third-order delta-sigma modulator.
The third integrator is shown in Figure 10. Its schematic is similar to that of the first integrator. The sampling and integrating capacitances are shown in the same figure.
Figure 10: Third integrator of a delta-sigma modulator.
Understanding the OTA
Operational transconductance amplifiers (OTA) are critical in the design of delta-sigma modulators. High gain and high bandwidth OTAs are needed for the proposed modulator due to the SNR specifications and high clock rates.
Gain boosting techniques13 are employed in the design of OTA in order to acquire high gain and high bandwidth at the same time. The basic principle is that a DC gain enhancement can be acquired without affecting the gain and phase characteristics of the operational amp at high frequencies.
In order to meet the settling requirements imposed by a clock rate over 100 MHz while maintaining a low power consumption, a telescopic amplifier topology (Figure 11) is chosen for the main amplifier because of its good frequency response and relatively low bias current budget. The switched capacitor common-mode feedback (CMFB) circuit is used to track the output common-mode voltage level. The value of tail current, I_tail, is 590 μA for the main amplifier in the first stage. To save power, the value of I_tail can be scaled down by a ratio of 1/2 and 1/4 for the OTAs in the second and third stage, respectively.
Figure 11: Schematic of the OTA.
The auxiliary amplifiers are designed using the folded-cascade topology, which aims to provide sufficient DC gain enhancement. The CMFB loop is built by connecting the output nodes to gates of two large transistors, which are working in the linear region. The biasing plan is the following: (1) Individual biasing network is used for each main amplifier to provide sufficient isolation; (2) The auxiliary amplifiers in three integrators share the same biasing network in order to save power.
The simulated UGBW and phase margin (PM) of the OTA are 480 MHz and 56 degree, respectively. The simulated dc gain is 83 dB. The idea of the foregoing gain boosting scheme is that DC gain should be determined mainly by the folded-cascade auxiliary amplifiers, while the telescopic main amplifier is optimized for high bandwidth. The direct undesirable result of this configuration is a lower DC gain.
To alleviate this problem, a preamplifier can be added in front of the main amplifier14 as illustrated in Figure 12. A DC gain as high as 96 dB has been reported using this amplifier topology.15. However, this amplifier inevitably consumes more power than the previous one (extra 2 to 3 mW at a 2.5 V supply).
Figure 12: Schematic of the OTA with a preamplifier.
The single-bit quantizer is composed of a dynamic regenerative comparator and a static SR latch, as shown in Figure 13. The comparator is based on the design discussed in Reference 14 for the sake of low power consumption.
Figure 13: Schematic of a single-bit quantizer.
The comparator shown in Figure 13 is in the reset mode when the clock phase ck1e is low, and the outputs are set to V_DD by M_9 and M_10. When ck1e goes high, the comparator enters the regenerative mode, and M_3-M_8 form a positive feedback loop in order to amplify the input difference, which is sensed by M_1 and M_2, to a full-scale rail-to-rail output. Once the comparator makes a decision, the cross-coupled transistors will shut down all connections between V_DD and V_SS, which will cause null dc power consumption.
Figure 14 shows the simulated Fast Fourier transform (FFT) of the modulator for the GSM standard. An IF input signal at 15-kHz offset from the IF center frequency (78 MHz) is driving the modulator. The spectrum indicates that thermal noise is responsible for a 30-dB loss in overall SNR performance, and hence the noise floor seen here is dictated by thermal noise. The thermal noise floor is flat up to 100 kHz, which is half the signal bandwidth for GSM standard. A noticeable harmonic at 45 kHz (third-order) dictates the signal-to-noise and distortion ratio (SNDR) performance.
Figure 14: Output spectrum for a GSM modulator.
Figure 15 shows the simulated FFT of the modulator for the W-CDMA standard. An IF input signal at 100-kHz offset from the IF center frequency (138.24 MHz) is added. The spectrum indicates that thermal noise floor is higher than the quantization noise floor for frequencies up to 800 kHz. The thermal noise floor is roughly flat up to 2 MHz, which is half the signal bandwidth for W-CDMA standard.
Figure 15: Output spectrum for a W-CDMA modulator.
Figure 16 shows the simulated FFT of the modulator for the DECT standard. An IF input signal at 100-kHz offset from the IF center frequency (110.59 MHz) is driving the modulator. The spectrum indicates that thermal noise floor is higher than the quantization noise floor for frequencies up to 300 kHz. The thermal noise floor is roughly flat up to 576 kHz, which is half the signal bandwidth for DECT standard. A noticeable harmonic at 300 kHz (third-order) limits the SNDR performance.
Figure 16: Output spectrum for a DECT modulator. Figure 17
illustrates the simulated SNDR vs. input amplitude level curves for all three standards. As shown, the simulated peak SNDR values are 80.1 dB (GSM), 55.3 dB (W-CDMA), and 64.9 dB (DECT). The simulated dynamic range values are 90 dB (GSM), 70 dB (W-CDMA), and 76 dB (DECT).
Figure 16: SNDR vs. input for the GSM, DECT, and W-CDMA modulators
The post-layout simulation results of the proposed modulator are given in Table 3
. For comparison purposes, the modulator specifications reported in references 16 and 17 are also listed.
Table 3: Comparison of simulated performance
As Table 3 shows, the dynamic range performance of this single-loop modulator is worse than that reported in Reference 16, where a cascaded (MASH) 2-2 topology was used at a price of, however, much higher power consumption (65 mW in total for GSM/DECT applications with a 3.3 V supply).
Having demonstrated the post-layout simulation results, it is instructive to mention the chip-level test plan, since the receiver is already in the process of fabrication (a standard 0.35-μm, 2.5-V, DP5M CMOS process in this case). During the test, a fully differential sinusoidal input signal (i.e., the IF signal) will be off-chip bandpass filtered before entering into the modulator. The digital output will be acquired with a test board, and the acquired data stream will then be transferred to a workstation for spectral analysis.
The clock for the modulator will be generated from an off-chip RF pulse generator and brought onto chip through a bond-pad and then amplified to a 2.5 V rail-to-rail swing. Although there are band-gap references available on-chip, a clean off-chip voltage reference should be used for the modulator measurement, for the purpose of diminishing the effect of distortion due to an unclean reference.
This article showed the feasibility of achieving high IF signal digitization using a pair of low-pass delta-sigma modulators. While this discussion has provided some interesting technical benefits, additional work is still needed. First, future work is needed to explore the interaction between IF filter and the baseband ADC needs since the dynamic range requirements of the ADC will be relaxed in the presence of a high-attenuation IF band-pass filter. Second, It's well known that cascaded delta-sigma modulators suit for wideband baseband applications, but at the same time, consume more power and area than single-loop modulators do. Thus, efforts are needed to find the optimum balancing point, both on system and on circuit level. Finally, the design of the automatic gain controller (AGC) may be associated with that of the delta-sigma modulators for the sake of high integration, since they have similar dynamic range and linearity requirements. Editor's note: To view Part 1 of this article, click here.
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About the Author
Mingliang Liu is a product development manager at Extron Electronics. Prior to this position, he served as a product manager at AV Link, Inc. He holds a B.S.E.E. degree from Beijing Institute of Technology and a M.S.E.E. degree from Oregon State University. Mingliang can be reached at firstname.lastname@example.org.
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