A new paradigm in embedded design has arrived, driven by the steady increase in the capability of field-programmable gate arrays (FPGAs), which now have the equivalent of over a million logic gates. With these resources it is now possible to implement complex digital systems, including one or more microcomputers, inside a single FPGA. System-on-chip devices can be produced by other than specialized ASIC designers since the embedded-system designer now has exciting new opportunities along with daunting challenges.
Many programmable logic companies have introduced devices that allow the user to combine general-purpose processing with programmable logic on the same chip. Some of these devices include a dedicated hard-core microcontroller with FPGA-based logic, while others, such as Xilinx's MicroBlaze, rely on a soft-core microcontroller that can be implemented inside an FPGA with user logic.
Xilinx provides tools for implementing both PowerPC and MicroBlaze processors within its FPGAs. Although the MicroBlaze will typically be programmed in C/C++, it is helpful if not necessary for a designer to thoroughly understand the MicroBlaze architecture. Xilinx provides extensive online documentation of Micro-Blaze and development tools at www.xilinx.com. The material in this and the following section was obtained primarily form the Micro-Blaze Processor Reference Guide there.
MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx FPGAs. The MicroBlaze consists of thirty-two 32-bit general-purpose registers, R0 to R31, and two 32-bit special purpose registers. The special-purpose registers are the program counter and the machine status register. The general-purpose register R0 is also special because when it is read the value returned is always 0. Other general-purpose registers, such as R14, R16 and R17, have special purposes in servicing interrupts, exceptions and breaks. The instructions are 32 bits and are divided into two types, A and B. Type A instructions usually have two source registers and one destination register; Type B instructions contain a 16-bit immediate value, along with a source register and a destination register.
The MicroBlaze instructions are executed in a three-segment pipeline consisting of fetch, decode and execute stages. The pipeline effectively enables one instruction per clock cycle to be executed except in cases like branches where the normal pipeline flow is disrupted. Delayed branches are provided to reduce the branch penalty.
Memory is byte-addressable and memory accesses must be data-size-aligned. For half-word access the least significant bit of the address is forced to 0, and for byte access the two least significant bits of the address are forced to 00. Note that MicroBlaze is a Big Endian processor.
It is possible to implement instruction and data caches and the user has considerable flexibility in how these are configured. MicroBlaze also features a debug interface to support JTAG-based software debugging tools.
To begin development of MicroBlaze applications the minimum set of tools needed consists of the Xilinx Embedded Development Kit, the Xilinx Integrated Synthesis Environment and a hardware-development board.
The development kit and synthesis environment software can run on Windows 2000, Windows XP or Solaris 2.8/2.9. The MicroBlaze can be implemented in various Xilinx FPGAs ranging from Spartan II to Vertex II Pro devices. Because of the FPGA resources required by the MicroBlaze, it is probably unreasonable to select devices with less capability than the Spartan IIE, even as a learning platform. For serious applications, Vertex or Spartan III devices should be selected. Hardware development boards can be obtained from several sources, including Avnet, Digilent, Memec Design and Xilinx.
So are FPGA soft cores the microcontrollers of tomorrow? The answer is that it is unlikely that they will entirely replace conventional microcontrollers; however, the advantages offered by this emerging trend are so great that in the future we expect it to be a dominant technology that cannot be ignored by embedded system designers.
Jerry H. Tucker(firstname.lastname@example.org) and Robert H. Klenke (email@example.com)are associate professors of electrical engineering and computer engineering at Virginia Commonwealth University (Richmond, Va.). Gene S. Monroe (firstname.lastname@example.org) is a design engineer at NASA Langley Research Center (Hampton, Va.).
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