RF CMOS challenges in SoC Implementation

Designers creating the analog/RF portion of system-on-chip designs need considerable additional support from the foundry. Take one simple component, the inductor, to illustrate the depth of these needs.

A set of spiral inductor libraries, or metal-insulator-metal or metal-oxide-metal capacitors, are built into the design kit. With this, the layout and an electrical model can be generated.

This is a big help to the designer. However, some input from the foundries is still needed for successful analog design tapeouts. For example, most foundries provide only corner-case device models for device modeling, which are good enough for digital design but often not suited for analog/RF designs. A more desired model library should included corner case, statistical models, digital/analog mismatch models, pad models with RF electrostatic discharge, flicker-noise models, substrate resistance models and well-proximity and shallow-trench isolation stress effects.

For many years, some foundries provided only a set of spiral inductor libraries while others provided only libraries of square ones. Ironically, while spiral inductors are used throughout RF ICs, rarely would the design engineer adopt the inductor from a foundry design kit.

UMC provides hexagonal, circular and square inductors for its various processes. Why do some designers use a hexagonal spiral, others prefer a circular spiral and still others prefer squares--while some prefer single-end? The way to satisfy all customer requests is not to provide various sizes, shapes and symmetrical/single-end spirals; that approach could be endless and futile.

For a design house to create a spiral inductor for different designs, the engineer usually needs to model the process layer to accommodate an electromagnetic (EM) simulator, such as HFSS from Ansoft or ASITIC from the University of California at Berkeley. Then a silicon test structure is fabricated and measured, and a model is created for simulation. This process is often reiterated several times. This is time consuming, taking a huge part of the development cycle, so it can be extremely expensive. Since all customers need to go through this development process, a smart foundry should help its customers skip these reiterative steps. UMC's approach was to develop an electromagnetic design methodology (EMDM) that augments third-party EDA analog/RF design flows.

Since the electrical model library has shown that it does not serve its purpose well, UMC decided to provide a process-layer model targeted at various EM simulators and benchmark it against measurement data. With this process-layer model, every customer can easily generate various inductors to address the intended use in its design and the design methodology can keep the cost and development time down to a minimum. First, a process-layer model is prepared to target designers' preferred process implementations. Next, a set of test structures is created for 3-D EM simulation. The resulting s-parameter is then compared with wafer measurement results; from here, an electrical model can be extracted from the s-parameter.

As a lot of questions can be raised about the accuracy and simulation time for the EM simulator, UMC selected the well-known EM simulator HFSS. By incorporating an innovative process-model approach UMC can reduce the time needed for a true 3-D simulation from more that 20 hours to less than 20 minutes.

EMDM can be further applied to all passive structures within RF ICs, including: capacitors, transformers and complex layout analysis such as signal metal trace crosstalk and signal integrity. Furthermore, models of pc-board traces, IC packaging, flip-chip solder bumps and bond-pad and bond-wire can be analyzed within a standard design flow. For example, various layouts can be linked directly together for simulation by HFSS, or they can be imported to a GDSII file whereby EM simulation can then be done with greater accuracy and speed. With a few clicks on the pulldown menu, layout is transferred to HFSS.

When analog/RF design and foundry support are well tied together, SoC integration can be more readily achieved. It is clear that system specifications within varying operating frequencies, transmission methods, digital modulations, signal-to-noise ratios and data rates will require different design considerations and architectures.

For different systems, the degree of challenge will vary. Some of the most successful RF CMOS SoC products found in the market today are concentrated on Bluetooth and 802.11b, among them SiliconWave's UltimateBlue's SiW3500, Broadcom's MCM2033B1 and Cambridge Silicon Radio's BC212015. Since they have lower data rate requirements, they are easier to implement as RF CMOS ICs. For other more stringent system requirements, more integrated SoCs will be coming to market soon. While foundry architectures and sophisticated design methodologies for complex mixed-mode systems are available now, they continue to undergo constant innovation. This innovation will allow purely analog and RF components to not only come to market faster, they will do so in the same process generations as their digital IC counterparts.

Albert Yen (Albert.Yen@umc-usa.com) is manager of mixed-mode technologies at UMC (Sunnyvale, Calif.).

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