During the last three years, the mixed-signal system-on-chip (SoC) market has grown consistently. Industry analyst firm IBS Corp. estimates that by 2006, more than 70 percent of all SoCs will contain some analog components. However, that analog and digital circuitry must co-exist in a single substrate deepens the need to shorten the design time for analog circuitry.
While the design of digital circuits is highly automated, analog designers are still using the same Spice-simulation-based design flow as they were 30 years ago. This laborious design process is iterative in nature and needs to be repeated at every SoC silicon technology node. In recent years, analog designers at Barcelona Design have tried an approach based on actually capturing design intent into equation-based synthesizable analog models (SAMs). A SAM encapsulates the designer's domain expertise by capturing the "unsized" circuit topology and design constraints into an equation-based description language.
The method has successfully been applied to popular analog and mixed-signal circuit topologies, such as op amps, ring-oscillator-based phase locked loops (PLLs) and now to a high-speed pipeline analog-to-digital converter (ADC).
A SAM essentially captures the intent of the circuit designer and a layout designer. The constraints to satisfy the required performance and functionality are described in terms of a "geometric programming"(GP) optimization problem. Similarly, the constraints for routing the layout are specified in GP. In addition, GP device models (NMOS/PMOS transistor, poly resistor, metal capacitor, etc.) and physical information for the process (i.e. LVS/DRC rules, via, antenna rules, etc.) are included as a part of the problem set. This allows for simultaneous device sizing and layout generation.
We found that when we used a one-time modeling effort to describe a circuit topology in this way, our model generated highly-complex customized analog and mixed-signal modules very quickly in comparison to SPICE-acceleration methods — literally from spec to layout within a day. A single run took into account process/voltage/temperature (PVT) variations, thereby avoiding iterative Spice-and-tweak simulations over corners. Further, since device and circuit-topology components of our model were separate, we could easily port SAMs between silicon processes by updating only their device- and physical-level components.
Designing the ADC
We designed a pipeline ADC SAM that was used to tape out four instances (at 1, 30, 80 and 100 Msamples/second) on TSMC's 0.13-micron generic logic process. This was the first time in the industry a circuit with the complexity of a high-speed ADC was automatically synthesized, from spec to GDSII.
The speed differential was dramatic: with the SAM model developed, we created these final designs over one weekend. By comparison, when we manually taped out a single 10-bit 80-Msample/s instance to prove the topology, the design and layout phase took five months.
The synthesized topology we used was the well-known "1.5 bit/stage" single-pipeline architecture, consisting of an internal sample-and-hold (SHA) circuit, eight conversion stages each generating 1-bit+ redundancy, and a final 2-bit flash ADC stage. The redundancy made the structure insensitive to circuit imperfections.
| Using equation-based synthesizable analog models to capture the intent of the circuit designer and a layout designer can greatly accelerate the design of complex analog functions such as a pipeline A/D. |
We implemented each stage using a switched-capacitor structure. As a bucket brigade, capacitors sampled the incoming analog signal, held a signal value in each stage while generating a partial digital output and passed the analog residue — after amplification — to the next stage. The SAM model sized the SHA and pipeline components of the ADC automatically based on user-input specifications such as signal-to-noise ratio (SNR), ADC sampling rate, linearity, power and area constraints.
For SNR, we set an upper limit to achieve SNR by the total amount of thermal noise generated by the circuit. For capacitors, thermal noise is inversely proportional to capacitor size (noise is approximately equal to kT/C). The pipeline ADC SAM took into account the SNR input specification and translated this system requirement into requirements on individual device sizes. We chose a larger sampling capacitor with a higher SNR requirement because of its lower thermal noise. However, we found that increased performance came at the expense of higher power consumption and larger layout area.
Since the ADC SAM included layout generation, we could accurately estimate the effect of device size changes on area and aspect ratio. Such a comparison shows the dramatic effect of a higher SNR requirement on the pipeline ADC's total power consumption. This is an example of trade-off analysis: a graph can be quickly constructed in which each point represents a design completed via automated ADC synthesis. While no designer would attempt to achieve this with a manual approach because of the required design time for each alternative, automated synthesis made such an evaluation of different candidate circuits practical.
We used four steps to validate the ADC model. First, we used the ADC SAM to generate a large number of unique designs based on varying input specifications and operating conditions. We did this to ensure that in every case, a valid design and layout was generated. This test also included DRC and LVS checks on the automatically generated layout.
Second, we ran circuit simulations on key sub-blocks of the design. In particular, for the ADC SAM, we simulated distortion due to the sample-and-hold circuit and the sampling switches, and we performed an ac analysis of all op amps.
Third, we ran full-chip circuit simulations with and without extracted parasitic capacitances to check overall functionality and performance of the ADC.
Fourth, we compared the performance of the silicon obtained from a synthesized design against the earlier manual 10-bit 80-Msample/s hand design. We achieved THD (total harmonic distortion) performance of 59 dB, compared with 65 dB in the earlier manual design. Since the time of tape-out, October 2003, several improvements in automatic layout creation have been incorporated to reduce this difference. In particular, the router has been enhanced to limit parasitic capacitances.
Bart DeCanne(firstname.lastname@example.org) is a product manager and Vaishali Nikhade(email@example.com) is staff engineer at Barcelona Design (Santa Cruz, Calif.).