A new approach to jitter testing has been devised for leading-edge systems. It takes a spectral view of the jitter that not only allows immediate identification of the sources for debugging but also permits frequency-selective testing of jitter for production purposes. Overall, the test method lets test engineers quickly verify and improve the jitter performance of highly complex systems-on-chip by using IC automatic test equipment (ATE) and bit-error-rate testers.
This method extracts the frequency information of parasitic jitter components and makes it possible to quantify the spectral jitter components with respect to jitter energy. Given a mixture of random and periodic jitter, the method is able to extract the deterministic portion even though it is deeply buried in the random jitter.
Massive parallel embedding of high-speed I/O ports running at multiple gigabits per second is being used to match the lagging I/O bandwidth of system-on-chip devices to the constantly growing performance of digital logic cores. As a result, managing crosstalk from millions of simultaneously switching transistors, many of them injecting unwanted jitter into the sensitive analog circuits, is one of the toughest challenges facing high-speed I/O technology.
Jitter induced by ground bounce and clock crosstalk is a particularly difficult problem, since it cannot easily be simulated. And since a product often can't wait to be fully optimized for its jitter performance to be characterized, production usually starts while process variations can still critically affect performance. This is what makes an efficient jitter test methodology in design verification and early production so important.
To do this, the jitter needs to be separated into its frequency or spectral-density components. ATE for ICs as well as parallel bit-error-rate testers is readily available to stimulate the device under test with high-speed data and to compare the device response at speed.
This equipment is required to verify critical parameters such as the bit-error rate (BER) to confirm compliance with key standards or proprietary specifications. The method introduced here employs IC ATE as well as bit-error-rate testers (BERTs) to give insight to the spectral composition of jitter.
When conventional BER measurements are made on a data signal, the goal is to find a threshold and a sampling point for comparison such that the BER is zero, or at least minimized. Typically, this sweet spot is within the center of the data eye. However, the proposed method offsets the sampling point into the crossover section of the data eye. An error signal is the result of the comparison between the incoming data and the expected data. This error signal gained from sampling at the crossover is no longer a simple pass-fail result; instead, it contains the frequency information of the actual jitter even after digitizing. In contrast, a histogram basically destroys any frequency information.
The spectral decomposition is obtained from the error signal with the help of digital signal processing tools. In the generic case of mixed random jitter and deterministic periodic jitter, the spectral decomposition can show different categories of jitter: Of these, random jitter causes a broadband jitter spectrum, eventually shaped by a phase-locked-loop (PLL) filter indicating the corner frequency. For its part, deterministic periodic jitter causes one or more discrete peaks that cannot be tracked by clock data recovery (CDR) methods.
Because the spectral power density of the random portion gets distributed over many frequencies, while the spectral power of the periodic portions stays concentrated in discrete lines, the detection of spurious periodic jitter deeply buried in random jitter is significantly enhanced. Thus, even the smallest sources of periodic and deterministic jitter can be identified.
To demonstrate the methodology, we inserted artificial jitter into the output of a system under test containing a high-bandwidth voltage-controlled delay line. A parallel BERT generates and analyzes a pseudo-random binary sequence data signal at 3.125 Gbits/second. To achieve a controlled jitter injection, an arbitrary waveform generator issuing a sinusoidal signal and a high-bandwidth noise generator are used for delay modulation.
A closed eye-with the help of composite modulation consisting of a sinusoidal component-injects about a 0.04-unit interval (13-ps) peak-to-peak jitter. Examining the statistical properties of the modulation signal, it becomes obvious that adding the noise signal to the sinusoidal deterministic signal completely supersedes the statistical parameters of the sinusoidal component. Even though the sinusoidal peak-to-peak value nearly equals the rms value of the noise, the sinusoidal component gets buried in the noise. Thus, any frequency information of the sinusoidal jitter source is lost in the histogram view.
The spectral decomposition result from a PCI Express TX prototype unit in compliance mode clearly shows the PLL roll-off and several discrete peaks from deterministic jitter (see figure, page 55). In this case, the TX output signal of the PCI Express device is fed into a CDR circuit to extract a clock from the data signal, as PCI Express does not provide a clock at the data rate. The device shows a peak of crosstalk from an internal clock running at 187.5 MHz. This information is extremely helpful for the designer in helping to locate the problem area.
Rainer Plitschka (email@example.com) is an application consultant with the Electronics Products Solutions Group of Agilent Technologies Inc. (Boeblingen, Germany).