Low-power memory system for 3G designs

With the need to process increasing amounts of audio and video data, third-generation (3G) wireless devices now need mass storage along with significant performance and low power consumption. From a technical perspective, the move from simple flash, or SDRAM-based designs, to double-data-rate (DDR) memory systems is a significant challenge on its own, but the added requirement for extracting higher performance from these new devices while managing power states requires significant expertise and resources.

In general, the three main sources of power consumption in these memory systems include the power consumed by the memory devices, power consumed by the clock activity and power consumed by the DDR DRAM controller logic itself. Achieving an optimally low-power memory system requires a memory controller design that addresses all of those issues. Add to this time-to-market pressures and the fact that the memory system has no differentiating value for the end product, and designers have the perfect case for acquiring intellectual property (IP) for their 3G design.

Standard DDR memory devices do offer some power-saving features, such as self-refresh modes. But nothing comes for free, and using the advanced power-saving modes of these specialized DDR devices requires the designer to build more intelligence into the memory controller logic. Fortunately, major memory vendors such as Elpida, Infineon, Micron and Samsung have developed specialized memories like Mobile DRAM that deliver the performance of DDR devices while incorporating power-saving modes and functionality for 3G-type applications. In addition, the new mobile memories don't include the power-hungry delay-locked loop (DLL) found in typical DDR devices.

In a standard DDR device, the purpose of the DLL is to constrain the data output timing with respect to the clock of the DRAM, reducing skews in the system. Lacking the DLL, the new low-power devices exhibit a much broader skew in the data timing relative to the DRAM clock. In turn, this adds significant complexity to the read capture logic that has to be developed by the memory controller designer.

There is also now a need for a DLL circuit in the memory controller itself. The designer must come up with a new architecture for this DLL function that uses less power but retains the functionality and timing to satisfy the DDR send-and-capture requirements in the 3G system.

Gating controls
To conserve power, memory controller designers also have to control the gating of clocks to the memories, and to the controller itself. Ideally, the memory controller would incorporate a scheme for automatically transitioning into various levels of power-saving modes, depending on the activity of the system.

The memory controller might implement this simple scheme to reduce power consumption from the controller and the memory devices in a series of stages:

Mode 0: Normal operation-no power-saving modes activated.

Mode 1: Memory is put in power-down mode, and is reactivated only when a refresh is required.

Mode 2: Memory is placed in power-down mode, and the clock to the memory is gated. Once a refresh is issued, the memory is returned to power-down mode, and the clock is again gated off.

Mode 3: The memory is placed into self-refresh mode, and the controller does not actively issue any commands. In this mode, additional logic can be used to control partial array refresh for additional power savings.

Mode 4: The memory is placed into self-refresh mode, and the clock to memory is gated off.

Mode 5: In this maximum power-saving mode, the memory is placed in self-refresh, and the memory clocks are gated off.

In addition to automatically controlling power modes, the controller must also provide a mechanism to enable software or firmware designers to force the memory system into any particular mode based on the anticipated activity in the system.

Michael McKeon (mike@denali.com) is the director of strategic products at Denali Software Inc. (Austin, Texas).