| Power consumption is a major source of pain for emerging complex SOC designs, particularly in battery sensitive applications requiring ultra low power. Not surprisingly, this area was the topic with the largest number of paper submissions at the DATE conference in Paris this year. The power pain will accelerate when moving to nanometer technologies with increased transistor counts and densities. |
New design techniques and methodologies are needed to control and limit this power consumption, and once again standard cells are at the heart of the issue. These building blocks of modern IC design are right in the middle of things, and quite possibly the cause of many power consumption aches and pains, but this challenge is also an opportunity for significantly lowering power.
Today's typical synthesis and place-and-route flow employs a coarse-grained set of library cells used to map a given design into its final physical implementation. The number of cells — and therefore the amount of optimization that can be done — is limited. Optimizing the cells to suit the design is a complicated process, because the optimum choice of standard cell drive-strength depends on the context of the cell, including the load of the cell and the drive-strength of the previous stage.
Larger drive strengths drive their load faster, but they load and slow the previous stage, while consuming more power. Having a limited set of choices produces a design that has longer cycle times, uses more power, and uses more area than a fully optimized design.
This approach, while considerably less efficient than full-custom design, is required for a fully automated design flow. Most of the SPR tools are focused on timing, so most standard cells used in a design are over-driven with excessive drive strengths. A recent study of 130 nanometer designs ranging from CPU cores to graphic chips to general-purpose controllers showed a transistor size surplus of 25-30% and more. 90nm designs will increase the trend with double transistor counts and increased leakage current due to thinning oxide and other process recipe changes.
Solution for today: Given the current commercial SPR flow, entrenched customer methodologies, and inherent fear of risk, a quick solution is to focus on power during SPR while relaxing timing constraints, then address the critical paths during static timing analysis (STA) and regain timing. This micro approach will only increase the drive strengths in the critical paths, thus meeting timing targets and reduces overall power and area.
A more aggressive approach is to replace all cells after STA with L (low power) or half drive strength cells, then fix timing by increasing only the drive strengths in the critical paths required for meeting timing. There are commercially available, automated point tools for both these methodologies that fit seamlessly into the standard SPR flow.
Solution for tomorrow: Do it right the first time by enabling SPR tools to detect and correct over-driven paths during RTL. This will result in a pre-optimized gate level place and route. In addition, compensate for the restrictions of coarse-grained standard cell drive strengths by giving SPR tools greater control over the standard cells and library requirements.
If optimizing during STA yields double-digit results in timing and power, how much more pain (including design time and money) can be eliminated by further empowering today's physical synthesis, place-and-route tools?
Dan Nenni is vice president of sales and marketing at Prolific, Inc.