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Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
New Approach Combines ASIC and FPGA Benefits
eeProductCenter (Jul 27 2004, 12:00 PM)
Design teams all over are debating. While time to market and risk can be substantially lowered by going the FPGA route, the ASIC path carries potential benefits that can't be ignored. An ASIC implementation can for the most part, always map functions and logical blocks more efficiently that those implemented in generic logic granules. The ultimate attainable performance can be higher with a custom tailored implementation on an ASIC. And, if every 't' is crossed and every 'i' is dotted, the cost for an end product can be substantially lowered.
But, FPGAs allow the same product to be updated more easily. If there are any mistakes, or even better ways to implement a design after the initial product release, it simply means a new 'fusemap' code to upgrade the functionality or performance. This can also be beneficial say if an early flavor of a design implements an emerging standard. As the standard is improved or embellished, it can be easier in an FPGA to upgrade the functionality.
Design teams all over are debating. While time to market and risk can be substantially lowered by going the FPGA route, the ASIC path carries potential benefits that can't be ignored. An ASIC implementation can for the most part, always map functions and logical blocks more efficiently that those implemented in generic logic granules. The ultimate attainable performance can be higher with a custom tailored implementation on an ASIC. And, if every 't' is crossed and every 'i' is dotted, the cost for an end product can be substantially lowered.
But, FPGAs allow the same product to be updated more easily. If there are any mistakes, or even better ways to implement a design after the initial product release, it simply means a new 'fusemap' code to upgrade the functionality or performance. This can also be beneficial say if an early flavor of a design implements an emerging standard. As the standard is improved or embellished, it can be easier in an FPGA to upgrade the functionality.
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