Inside the HyperTransport 2.0 Interface

HyperTransport has proven to be a powerful, integrated parallel chip-to-chip interconnect technology that can provide performance benefits to a wide range of applications while simplifying board-level design. With the move to HyperTransport 2.0, however, the specification has increased the bandwidth by 75 percent, further extending its sphere of application.

When introduced in 2001, the HyperTransport 1.03 specification defined an aggregate bandwidth of up to 12.8 Gbytes/second, far exceeding any other I/O technology at that time. The latest 2.0 specification supports a 22.4-Gbyte/s aggregate bandwidth that yields the highest bandwidth in the industry as of mid-2004.

To get to these rates, HyperTransport employs dual point-to-point unidirectional data links — one for input and one for output — with a concise signal set using 1.2 V low-voltage differential signaling (LVDS). It carries both standard computer-based load/store data and communications-oriented user packet data in HyperTransport packets.

The HyperTransport dual links include a data path (2, 4, 8, 16 or 32 bits wide), one or more clock lines (one for each 8-bit data path) and a single control line. Commands, addresses and data are carried in packets over the data path, eliminating many sideband control signals needed in traditional multiplexed, multidrop bus standards such as PCI and PCI-X.

The use of differential signaling in HyperTransport yields higher noise immunity and speed. In addition, since HyperTransport is packet oriented with only a few sideband signals, it has many fewer pc-board traces than traditional single-ended buses. The HyperTransport's typical differential output is 600 mV and the differential voltage at the receiver can be as low as 300 mV.

The 2.0 update
The HyperTransport 2.0 specification adds three new speed grades — 2.0, 2.4, and 2.8 Gigatransfers/s. For the two highest speeds, the transmitter uses a simple de-emphasis circuit that uses a 1-bit history to de-emphasize the differential amplitude generated by the transmitter by 33 percent at 2.8 Gtransfers/s when transmitting a continuous run of 1s or 0s.

This de-emphasis adds a high-pass filter to the output that counteracts the low-pass filter created by the pc-board material at high frequencies. The combination of these two filters produces a smaller but cleaner eye at the receiver. Since the eye is smaller at the receiver end, the receiver must have a higher sensitivity of 200 mV to support these two highest rates.

A typical implementation of the transmitter adds a second pair of pull-up and pull-down transistors to each leg of the output. When the full voltage is needed, both pull-up or pull-down transistors are used. When the de-emphasized voltage is needed, only one set is used.

The table of pc-board trace skews that existed in the specification was extended to allow for the three added speeds. These skews are very achievable, particularly with the help of the pc-board design software tools that are available.

It is important to note that HyperTransport 2.0 devices operate smoothly with HyperTransport 1.0 devices. To facilitate this, HyperTransport interfaces initially boot up at 200 MHz and advertise their frequency capabilities to each other. Software automatically determines the highest mutually supported frequency for the two ends and configures each to run at that frequency. There is also a similar mechanism to negotiate the width of the link.

HyperTransport has been widely adopted across a wide spectrum of high-performance products ranging from consumer devices to personal computers, servers, network equipment and supercomputers. Specifically, it has been used in the Microsoft Xbox, several routers from Cisco Systems, servers from IBM and Sun Microsystems, notebooks and tablet PCs based on Transmeta's Efficeon processor, all PCs and servers based on AMD's Athlon64 and Opteron processors, as well as Cray and IBM supercomputers.

In many cases, HyperTransport's integration extends into the processor, such as in the AMD Opteron and Athlon64 64-bit x86 processors, Transmeta's Efficeon x86 processor, Broadcom's BCM1250 64-bit MIPS processor, and PMC-Sierra's RM9000 64-bit MIPS processor family. In these instances, HyperTransport operates as a front-side bus. In other instances, such as in Apple's G5 PowerMac, HyperTransport is used as an integrated, high performance I/O bus that pipes PCI, PCI-X, USB, Firewire and audio/video links through the system. In all cases, HyperTransport replaces the overlapping processor and local I/O buses of earlier generation systems with a unified architecture.

Brian Holden (brian_holden@pmc-sierra.com) is technical chair of the HyperTransport Technology Consortium and principal engineer at PMC-Sierra Inc. (Santa Clara, Calif.).

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